Xilinx Virtex UltraScale+ FPGAs User Manual page 105

DFE/
RX EQ ADC
FFE
RX PMA
RX Serial Clock
The GTM receiver includes an RX FIFO to support data width conversion when data crosses from
the XCLK to TXUSRCLK domain, and the table below shows the possible scenarios. The buffer
does not tolerate ppm differences and only provides phase compensation between the two
clocks. The RX buffer inside the GTM transceiver must always be used. Buffer bypass is not
allowed.
Table 63: RX FIFO Data Width Conversion Scenarios
PMA Parallel Clock (XCLK) Domain
Data Width
Ports and attributes
The following table defines the RX buffer ports.
Table 64: RX Buffer Ports
Port
CH[0/1]_RXBUFSTATUS[1:0]
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Figure 44:
To RX Parallel Data
(Near-End PCS Loopback)
Pre-
Coder
SIPO
RX PCS
PMA Parallel Clock (XCLK)
64-bit
128-bit
128-bit
Dir
Out
RX Clock Domains
Gray
Polarity
Encoder
PRBS
Checker
PCS Parallel Clock (TXUSRCLK)
Domain Data Width
64-bit
80-bit
128-bit
Clock Domain
RXUSRCLK RX buffer status:
Bit[1]: FIFO overflow status. A value of 1
indicates FIFO overflow.
Bit[0]: FIFO underflow status. A value of 1
indicates FIFO underflow.
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Chapter 4: Receiver
From RX Parallel Data
(Far-End PCS Loopback)
RX
FEC
FIFO
Device Parallel Clock
PCS Parallel Clock (RXUSRCLK)
FEC Support
No
Yes
No
Description
www.xilinx.com
RX
Interface
(RXUSRCLK2)
X20945-061418
105