Xilinx Virtex UltraScale+ FPGAs User Manual page 132

Table 74: GTM Transceiver PCB Design Checklist (cont'd)
Pins
1
VCCINT_GT[N]
1
MGTVCCAUX[N]
Notes:
1. N refers to different power supply groups in the package. See
Groups and RCAL Master
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
•
For UltraScale+ FPGAs, the nominal voltage is 0.85 VDC or 0.9 VDC.
•
See the UltraScale+ device data sheets (see http://www.xilinx.com/documentation) for power
supply voltage tolerances.
•
Many packages have multiple groups of power supply connections in the package for
VCCINT_GT. Information on pin locations for each package can be found in the UltraScale and
UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575).
•
The following filter capacitor is recommended:
1 of 4.7 μF ± 10% per power supply group (see
○
Power Supply Groups and RCAL
•
For optimal performance, power supply noise must be less than 10 mVpp.
•
If all of the Duals in a power supply group are not used, the associated power pins can be left
unconnected or tied to GND.
•
For power consumption, refer to XPE at www.xilinx.com/power.
•
For UltraScale+ FPGAs, the nominal voltage is 1.8 VDC.
•
See the UltraScale+ device data sheets (see http://www.xilinx.com/documentation) for power
supply voltage tolerances.
•
The power supply regulator for this voltage should not be shared with non-transceiver loads.
•
Many packages have multiple groups of power supply connections in the package for
MGTVCCAUX. Information on pin locations for each package can be found in the UltraScale
and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575).
•
The following filter capacitor is recommended:
1 of 4.7 μF ± 10% per power supply group (see
○
Power Supply Groups and RCAL
•
For optimal performance, power supply noise must be less than 10 mVpp.
•
If all of the QPLLs in this power supply group are not used but the Duals are used, the filter
capacitors are not necessary. These pins can be connected to V
•
For power consumption, refer to XPE at www.xilinx.com/power.
for the organization of power supply groups in each package.
Chapter 5: Board Design Guidelines
Recommendations
Figure 48: UltraScale+ Device Transceiver
Master)
Figure 48: UltraScale+ Device Transceiver
Master)
CCAUX
Figure 48: UltraScale+ Device Transceiver Power Supply
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