Xilinx Virtex UltraScale+ FPGAs User Manual page 80

Table 46: TX Configurable Driver Ports (cont'd)
Port
CH[0/1]_TXEMPPRE[4:0]
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Clock
Dir
Domain
Input Async Transmitter pre-cursor TX pre-emphasis control. The default is
user specified. All listed values (dB) are typical
[4:0]
5'b00000
5'b00001
5'b00010
5'b00011
5'b00100
5'b00101
5'b00110
5'b00111
5'b01000
5'b01001
5'b01010
5'b01011
5'b01100
5'b01101
5'b01110
5'b01111
5'b10000
5'b10001
5'b10010
5'b10011
5'b10100
5'b10101
5'b10110
5'b10111
5'b11000
5'b11001
5'b11010
Notes:
1. The peak-to-peak differential voltage is defined when
CH[0/1]_TXEMPPOST = 5'b00000, and
CH[0/1]_TXEMPPRE2 = 4'b0000. Emphasis =
20log10(V
Chapter 3: Transmitter
Description
dB (PAM4) dB (NRZ)
0.0 0.0
–0.3 –0.2
–0.7 –0.5
–1.1 –0.7
–1.5 –0.9
–1.9 –1.2
–2.3 –1.5
–2.7 –1.7
–3.2 –2.0
–3.7 –2.3
–4.2 –2.6
–4.8 –2.9
–5.4 –3.2
–6.0 –3.5
–6.7 –3.9
–7.5 –4.2
–8.3 –4.6
–9.2 –5.0
N/A –5.4
N/A –5.8
N/A –6.2
N/A –6.7
N/A –7.2
N/A –7.7
N/A –8.3
N/A –8.9
N/A –9.2
/V ) = |20log10(V /V
high low low high
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