Rx Fec - Xilinx Virtex UltraScale+ FPGAs User Manual

The following table defines the RX buffer attributes.
Table 65: RX Buffer Attributes
Attribute
CH[0/1]_RX_PCS_CFG0
CH[0/1]_RXFIFO_UNDERFLOW
CH[0/1]_RXFIFO_OVERFLOW

RX FEC

The Integrated KP4 Reed-Solomon Forward Error Correction (RS-FEC) provides a robust multi-bit
error detection/correction algorithm that protects up to 2 x 58 Gb/s or 1x116 Gb/s electrical and
optical links. This section describes the operation of the Integrated KP4 RS-FEC within the
UltraScale+™ device GTM transceivers.
KP4 FEC is based on the RS(544,514) code, which encodes message blocks of 5140 bits to
produce codewords of 5440 bits. For a detailed description of the RS-FEC sublayer in Ethernet,
including the definition of the KP4 FEC code, refer to clause 91 of the IEEE Standard for Ethernet
(IEEE Std 802.3-2015). The same FEC code is used in other standards such as OTN FlexO and
Interlaken.
The Integrated KP4 RS-FEC for each GTM dual is composed of two logical slices for each
channel. These can operate as two independent RS-FEC processing units at up to 58 Gb/s each,
or as one unified unit at up to 116 Gb/s. When operating at up to 116 Gb/s, data is transmitted
and received over four virtual FEC lanes as described in IEEE 802.3-2015 clause 91. When
operating as 2 x 58 Gb/s, data can be transmitted and received over two virtual FEC lanes per
58 Gb/s channel, or as a raw data stream (one virtual lane) with optional PN scrambling for
backplane operations. The general principle of operation of the FEC is the same whichever mode
is chosen.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Type
16-bit Binary Reserved. Use the recommended value from the
Wizard.
1-bit Binary A value of 1 indicates FIFO underflow.
For channel 0, bit[8] of DRP Address 0x48B.
For channel 1, bit[8] of DRP Address 0x68B.
:
Note This is a read-only attribute.
1-bit Binary A value of 1 indicates FIFO overflow.
For channel 0, bit[9] of DRP Address 0x48B.
For channel 1, bit[9] of DRP Address 0x68B.
:
Note This is a read-only attribute.
Chapter 4: Receiver
Description
www.xilinx.com
Send Feedback
106