Xilinx Virtex UltraScale+ FPGAs User Manual page 43

Table 19: Recommended Receiver Resets for Common Situations (cont'd)
Situation
After connecting RXN/RXP
After recovered clock
becomes stable
After RX elastic buffer error
After PRBS error
Eye Scan reset only
Notes:
1. RXPCSRESETMASK[1] can be set to 0 if the FEC is bypassed.
After Power-up and Configuration
The PLL being used and the entire GTM RX require a reset after configuration. See
Transceiver RX Reset in Response to Completion of
After Turning on a Reference Clock to the PLL Being
Used
If the reference clock(s) changes or GTM transceiver(s) are powered up after configuration,
perform a full RX sequential reset after the PLL fully completes its reset procedure.
After Changing the Reference Clock to the PLL Being
Used
Whenever the reference clock input to the PLL is changed, the PLL must be reset afterwards to
ensure that it locks to the new frequency. Perform a full RX sequential reset after the PLL fully
completes its reset procedure.
After Assertion/Deassertion of PLLPD for the PLL
Being Used
When the PLL being used goes back to normal operation after power down, the PLL must be
reset. Perform a full RX sequential reset after the PLL fully completes its reset procedure.
After Assertion/Deassertion of RXPD
After the RXPD signal is deasserted, perform a full RX sequential reset.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Components
to be Reset
RXRESETMODE RXPMARESETMASK RXPCSRESETMASK
Entire RX
2'b00
RX PCS
2'b11
RX PCS
2'b11
PRBS Error
2'b11
Counter
Eye Scan
2'b11
Chapter 2: Shared Features
Recommended RX Reset Setting
8'b11111111
8'b00000000
8'b00000000
8'b00000000
8'b00000000
Configuration.
Send Feedback
1
4'b1111
4'b1111
4'b1111
4'b1000
4'b0001
GTM
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