Xilinx Virtex UltraScale+ FPGAs User Manual page 16

PLLREFCLKSEL
GTNORTHREFCLK
GTSOUTHREFCLK
GTGREFCLK2PLL
Single External Reference Clock Use Model
Each Dual has one set of dedicated differential reference clock input pins (MGTREFCLK[P/N])
that can be connected to the external clock sources. In a single external reference clock use
model, an IBUFDS_GTM must be instantiated to use the dedicated differential reference clock
source. The following figure shows a single external reference clock connected to the LCPLL
inside the Dual. The user design connects the IBUFDS_GTM output (O) to the GTREFCLK ports
of GTM_DUAL.
:
Note The IBUFDS_GTM diagram in the above figure is a simplification. The output port ODIV2 is left
floating, and the input port CEB is set to logic 0.
The following figure shows a single external reference clock with multiple Duals connected. The
user design connects the IBUFDS_GTM output (O) to the GTREFCLK ports of the GTM_DUAL
primitives. In this case, the Xilinx implementation tools make the necessary adjustments to the
north/south routing as well as the pin swapping necessary to route the reference clock from one
Dual to another when required.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
LCPLL Reference Clock Selection Multiplexer
Figure 6:
0
GTREFCLK
1
2
3
4
5
6
7
Single External Reference Clock in a Dual
Figure 7:
IBUFDS_GTM
MGTREFCLKP I
MGTREFCLKN IB
GTM_DUAL
LCPLL
O
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Chapter 2: Shared Features
LCPLL Output CLK
X20897-061418
GTM_DUAL
GTREFCLK
X20898-061418
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