Xilinx Virtex UltraScale+ FPGAs User Manual page 103

Table 61: Pattern Checker Attributes (cont'd)
Attribute
CH[0/1]_RX_PCS_CFG1
Bit Name
RXPRBS_LINKACQ_CNT
The following table defines the pattern checker DRP read-only registers.
Table 62: Pattern Checker DRP Read-Only Registers
Attribute
CH[0/1]_RX_PRBSERR
Using RX Pattern Checker
The GTM RX pattern checker works for all supported data widths. However, 80-bit or 160-bit RX
fabric data width in PAM4 mode requires additional steps. Other data widths do not require any
additional steps.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Type
16-bit Reserved.
Address Description
[12:5] RX pattern checker link acquire count. Used in conjunction with
output port CH[0/1]_RXPRBSLOCKED. After the RX PRBS checker
has seen CH[0/1]_RX_PCS_CFG1[12:5] XCLK cycles of error-free
PRBS data, CH[0/1]_RXPRBSLOCKED is asserted High. The valid
range is 15–255.
Type
32-bit Binary PRBS error counter. This counter can be reset by
asserting CH[0/1]_RXPRBSCSCNTRST. When a single bit
error occurs in incoming data, this counter increments
by 1. Single bit errors are thus counted when multiple
bit errors occur in incoming data. The counter
increments by the actual number of bit errors.
Counting begins after RXPRBSLOCKED is asserted
High. The counter saturates at 32'hFFFFFFFF. This
error counter can only be accessed via the DRP
interface. Because the DRP only outputs 16 bits of data
per operation, two DRP transactions must be
completed to read out the complete 32-bit value. To
properly read out the error counter, the user must read
out the lower 16 bits first, followed by the upper 16 bits.
This read sequence must be followed:
Channel 0:
Channel 1:
Note
Chapter 4: Receiver
Description
Description
Upper 16 bits DRP address: 0x0483
Lower 16 bits DRP address: 0x0484
Upper 16 bits DRP address: 0x0683
Lower 16 bits DRP address: 0x0684
:
This is a read-only attribute.
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