Xilinx Virtex UltraScale+ FPGAs User Manual page 60

Similarly, the following figure shows the same settings in a multiple-lane configuration. In a multi-
lane configuration, the middle-most GTM transceiver should be selected to be the source of
TXPROGDIVCLK. For example, in a multi-lane configuration of six GTM transceivers consisting
of three contiguous Duals, one of the middle GTM transceivers in the middle Dual should be
selected as the source of TXPROGDIVCLK.
Multiple Lanes—TXPROGDIVCLK Drives TXUSRCLK and TXUSRCLK2 (64-Bit,
Figure 27:
UltraScale
Devices GTM
Transceiver
UltraScale
Devices GTM
Transceiver
Notes relevant to the figure:
1. For details about placement constraints and restrictions on clocking resources (such as
BUFG_GT and BUFG_GT_SYNC), refer to the UltraScale Architecture Clocking Resources User
Guide (UG572).
2. F = F
TXUSRCLK2
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
80-Bit, or 128-Bit Mode)
BUFG_GT
TXPROGDIVCLK
2
TXUSRCLK2
TXUSRCLK 2,3
TXDATA (TX data width =
64/80/128 bits)
TXUSRCLK2
TXUSRCLK 2,3
TXDATA (TX data width = 64/80/128 bits)
.
TXUSRCLK
1
2
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Chapter 3: Transmitter
Design in UltraScale
Architecture
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