Rx Cdr - Xilinx Virtex UltraScale+ FPGAs User Manual

RX CDR

The RX clock data recovery (CDR) circuit in each UltraScale+ FPGA GTM transceiver channel
extracts the recovered clock and data from an incoming data stream. The following figure
illustrates the architecture of the CDR block. Clock paths are shown with dotted lines for clarity.
RXP/N
The GTM transceiver employs the baud-rate phase detection CDR architecture. Incoming data
first goes through receiver equalization and ADC where the data is sampled. The sampled data
then moves through FFE and DFE before feeding to the CDR state machine and the downstream
transceiver blocks.
The LCPLL provides a base clock to the phase interpolator. The phase interpolator in turn
produces fine, evenly spaced sampling phases to allow the CDR state machine to have fine phase
control. The CDR state machine can track incoming data streams that can have a frequency
offset from the local PLL reference clock.
Ports and Attributes
The following table defines the CDR ports.
Table 52: CDR Ports
Port
CH[0/1]_RXCDROVRDEN
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Figure 40:
PLL PI
CTLE ADC
Adaptation
Dir
In
CDR Block Diagram
DFE
+
FFE
Clock Domain
Async Reserved. Use the recommended value
from the Wizard.
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Chapter 4: Receiver
Recovered
Clock
CDR FSM
RX Data
X20925-053118
Description
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