Xilinx Virtex UltraScale+ FPGAs User Manual page 35

Figure 18:
GTRXRESET
High
Wait until
GTRXRESET from
High to Low
RXPMARESETMASK[0]
= 1?
No
RXPMARESETMASK[1]
= 1?
No
RXPMARESETMASK[2]
= 1?
No
RXPMARESETMASK[3]
= 1?
No
RXPMARESETMASK[4]
= 1?
No
RXPMARESETMASK[5]
= 1?
No
RXPMARESETMASK[6]
= 1?
No
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
GTM Transceiver RX Reset State Machine Sequence
Yes
RX PMA Top
Reset
Yes
RX ADC CLKGEN
Reset
Yes
RX DSP Reset
Yes
RX DFE Reset
Yes
RX Adapt Reset
Yes
RX CDR PH Reset
Yes
RX CDR FR Reset
Chapter 2: Shared Features
Wait for
RXUSERRDY = 1
Yes
RXPCSRESETMASK[0]
= 1?
No
Yes
RXPCSRESETMASK[1]
= 1?
No
Yes
RXPCSRESETMASK[2]
= 1?
No
Yes
RXPCSRESETMASK[3]
= 1?
No
RXRESETDONE
High
Send Feedback
RX Eye Scan
Reset
RX FEC Reset
RX PCS Top Reset
RX PRBS Counter
Reset
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35