Xilinx Virtex UltraScale+ FPGAs User Manual page 15

From an architecture perspective, a Dual contains a grouping of two GTM channels inside one
GTM_DUAL primitive, one dedicated external reference clock pin pair, and dedicated reference
clock routing. The reference clock for a GTM_DUAL primitive must also be instantiated. For duals
operating at line rates lower than 16.3725 Gb/s (NRZ) and 32.7 Gb/s (PAM4), the reference clock
for a Dual can also be sourced from the Dual above via GTNORTHREFCLK or from the Dual
below via GTSOUTHREFCLK. For devices that support stacked silicon interconnect (SSI)
technology, the reference clock sharing via the GTNORTHREFCLK and GTSOUTHREFCLK ports
is limited within its own super logic region (SLR). Duals operating at line rates above
16.3725 Gb/s (NRZ) and 32.7 Gb/s (PAM4) should not source a reference clock from another
Dual.
See the UltraScale device data sheets (see
information about SSI technology.
Reference clock features include:
• Clock routing for northbound and southbound clocks.
• Flexible clock inputs available for the LCPLL.
• Static or dynamic selection of the reference clock for the LCPLL.
The Dual architecture has two GTM transceivers, one dedicated reference clock pin pair, and
dedicated north and south reference clock routing. Each GTM dual has three clock pair inputs
available:
• One local reference clock pin pair, GTREFCLK.
• One reference clock pin pair for the Dual above, GTSOUTHREFCLK.
• One reference clock pin pair from the Dual below, GTNORTHREFCLK.
The figure below shows the detailed view of a reference clock multiplexer structure within a
single GTM_DUAL primitive. The PLLREFCLKSEL port is required when multiple reference clock
sources are connected to this multiplexer. A single reference clock is most commonly used. In the
case of a single reference clock, connect the reference clock to the GTREFCLK ports and tie the
PLLREFCLKSEL ports to 3'b001. The Xilinx software tools handle the complexity of the
multiplexers and associated routing.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
http:/ /www.xilinx.com/documentation) for more
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Chapter 2: Shared Features
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