Xilinx Virtex UltraScale+ FPGAs User Manual page 44

RX Rate Change
When a rate change is performed, a full RX sequential reset is required after the rate attributes
have been updated.
RX Parallel Clock Source Reset
The clocks driving RXUSRCLK must be stable for correct operation. Perform an RX PCS reset
after the clock source re-locks.
After Remote Power-Up
If the source of incoming data is powered up after the GTM transceiver that is receiving its data
has begun operating, a full RX sequential reset must be performed to ensure a clean lock to the
incoming data.
After Connecting RXN/RXP
When the RX data to the GTM transceiver comes from a connector that can be plugged in and
unplugged, a full RX sequential reset must be performed when the data source is plugged in to
ensure that it can lock to incoming data.
After Recovered Clock Becomes Stable
Depending on the design of the clocking scheme, it is possible for the RX reset sequence to be
completed before the CDR is locked to the incoming data. In this case, the recovered clock might
not be stable when RXRESETDONE is asserted. When the RX buffer is used, a single mode reset
targeting the RX elastic buffer must be triggered after the recovered clock becomes stable.
Refer to the UltraScale+ device device data sheets (see
for successful CDR lock-to-data criteria.
After an RX Elastic Buffer Error
After an RX elastic buffer overflow or underflow, a sequential component reset targeting the RX
PCS must be triggered to ensure correct behavior.
After a PRBS Error
PRBSCNTRESET is asserted to reset the PRBS error counter.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Chapter 2: Shared Features
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