Xilinx Virtex UltraScale+ FPGAs User Manual page 30

GTM Transceiver TX Reset in Response to Completion
of Configuration
The TX reset sequence shown in
global GSR. It must meet these conditions:
1. TXRESETMODE must be set to sequential mode.
2. GTTXRESET must be used.
3. All TXPMARESETMASK and TXPCSRESETMASK bits should be set to High.
4. GTTXRESET cannot be driven Low until the associated PLL is locked.
5. Ensure that GTPOWERGOOD is High before releasing PLLRESET and GTTXRESET.
If the reset mode is defaulted to single mode, then you must:
1. Wait another 300–500 ns.
2. Assert PLLRESET and GTTXRESET following the reset sequence described in the following
figure.
RECOMMENDED: Use the associated PLLLOCK from the PLL to release GTTXRESET from High to
Low as shown in the figure. The TX reset state machine waits when GTTXRESET is detected High and
starts the reset sequence until GTTXRESET is released Low.
Figure 14:
GTM Transceiver TX Reset in Response to GTTXRESET
Pulse in Full Sequential Reset
The GTM transceiver allows you to reset the entire TX completely at any time by sending
GTTXRESET an active-High pulse. These conditions must be met when using GTTXRESET:
1. TXRESETMODE must be set to sequential mode.
2. All TXPMARESETMASK and TXPCSRESETMASK bits should be held High during the reset
sequence before TXRESETDONE is detected High.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
TX Initialization and Reset
GTM Transmitter Initialization after Configuration
Chapter 2: Shared Features
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