Xilinx Virtex UltraScale+ FPGAs User Manual page 34

TX Rate Change
When a rate change is performed, a full TX sequential reset is required after the rate attributes
have been updated.
TX Parallel Clock Source Reset
The clocks driving TXUSRCLK must be stable for correct operation. Perform a TX PCS reset after
the clock source re-locks.
RX Initialization and Reset
The GTM transceiver RX uses a reset state machine to control the reset process. Due to its
complexity, the GTM transceiver RX is partitioned into more reset regions than the GTM
transceiver TX. The partition allows RX initialization and reset to be operated in either sequential
mode, as shown in the following figure, or single mode:
1. RX in Sequential Mode: To initialize the GTM transceiver RX, RXRESETMODE must be set to
sequential mode. The RX components that are required to be rest are determined by setting
the appropriate RXPMARESETMASK and RXPCSRESETMASK bits to High. The reset
sequence is then triggered by toggling GTRXRESET and then internal component resets are
triggered sequentially. The reset state machine executes the reset sequence as shown in the
following figure, covering the entire RX PMA and RX PCS. During normal operation, the reset
state machine runs until RXRESETDONE transitions from Low to High.
2. RX in Single Mode: When the GTM transceiver RX is in single mode, RXRESETMODE must
be set to single mode. The RX components that are required to be rest are determined by
setting the appropriate RXPMARESETMASK and RXPCSRESETMASK bits to High. The reset
sequence is then triggered by toggling GTRXRESET and the internal component resets are
triggered simultaneously. In addition, RXADAPTRESET, RXADCCLKGENRESET,
RXBUFRESET, RXCDRFRRESET, RXCDRPHRESET, RXDFERESET, RXDSPRESET,
RXEYESCANRESET, RXFECRESET, RXPCSRESET, RXPMARESET and RXPRBSCNTRESET
pins are available to reset those components directly in single mode.
In either sequential mode or single mode, the RX reset state machine does not reset the PCS
until RXUSERRDY goes High. Drive RXUSERRDY High after all clocks used by the application,
including RXUSRCLK, are shown to be stable.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Chapter 2: Shared Features
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