Xilinx Virtex UltraScale+ FPGAs User Manual page 61

3. TXUSRCLK can be tied to 1'b0 if GEN_TXUSRCLK = 1'b1.
TXPROGDIVCLK Driving GTM Transceiver TX in 128-Bit, 160-Bit, or
256-Bit Mode
In the following figure, TXPROGDIVCLK is used to drive TXUSRCLK and TXUSRCLK2 in 128-bit,
160-bit, or 256-bit mode in a single-lane configuration. In all cases, the frequency of
TXUSRCLK2 is equal to half of the TXUSRCLK frequency.
Single Lane—TXPROGDIVCLK Drives TXUSRCLK and TXUSRCLK2 (128-Bit,
Figure 28:
UltraScale
Devices GTM
Transceiver
Notes relevant to the figure:
1. For details about placement constraints and restrictions on clocking resources (such as
BUFG_GT and BUFG_GT_SYNC), refer to the UltraScale Architecture Clocking Resources User
Guide (UG572).
2. F = F
TXUSRCLK2
Similarly, the following figure shows the same settings in a multiple-lane configuration. In a multi-
lane configuration, the middle-most GTM transceiver should be selected to be the source of
TXPROGDIVCLK. For example, in a multi-lane configuration of six GTM transceivers consisting
of three contiguous Duals, one of the middle GTM transceivers in the middle Dual should be
selected as the source of TXPROGDIVCLK.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
160-Bit, or 256-Bit Mode)
TXPROGDIVCLK
2
TXUSRCLK
TXUSRCLK2 2
TXDATA (TX data width = 128/160/256 bits)
/2.
TXUSRCLK
Chapter 3: Transmitter
BUFG_GT 1
÷2
BUFG_GT 1
÷1
Design in UltraScale
Architecture
X20913-111918
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