Xilinx Virtex UltraScale+ FPGAs User Manual page 75

Table 43: TX Programmable Divider Ports
Port
CH[0/1]_TXPROGDIVRESET
CH[0/1]_TXPRGDIVRESETDONE
CH[0/1]_TXPROGDIVCLK
Table 44: TX Programmable Divider Attribute
Attribute
CH[0/1]_TX_DRV_CFG4
Bit Name
TX_PROGDIV_SEL_FULLRATE
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir Clock Domain
In Async
Out Async
Out Clock
Type
16-bit Reserved.
Address Description
[15] This attribute is used during the TX programmable divider
ratio selection. Set to 1'b1 to obtain the full rate of the
divided clock. Set to 1'b0 to obtain the half rate of the
divided clock.
Chapter 3: Transmitter
Description
This active-High port resets the dividers as well
as the TXPRGDIVRESETDONE indicator. A reset
must be performed whenever the input clock
source is interrupted.
When the input clock is stable and reset is
performed, this active-High signal indicates the
reset is completed and the output clock is
stable.
TXPROGDIVCLK is the parallel clock output from
the TX programmable divider. This clock is the
recommended output to the interconnect logic
through BUFG_GT.
Description
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