Xilinx Virtex UltraScale+ FPGAs User Manual page 20

PLL
CLKIN
/M
The LCPLL VCO operates within 9.8 GHz—14.5 GHz. The Xilinx software tool chooses the
appropriate LCPLL setting based on application requirements.
determine the PLL output frequency (GHz).
Equation 2-2 shows how to determine the line rate (Gb/s).
Equation 2-3 and
Equation 2-1.
The table below lists the allowable values.
Table 8: LCPLL Divider Settings
Factor
M
N
LCPLLCLKOUT_RATE
Modulation
N
SDM
SDMDATA
SDMWIDTH
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Internal Dual Clocking Architecture
Figure 10:
Lock
Indicator
Phase
Charge
Frequency
Pump
Detector
/N-Fractional
f = f
PLLClkout PLLClkin
f = f
LineRate
Equation 2-4 show how to determine the fractional divider presented in
FractionalDivider = N
FractionalPart = SDMDAT A
Attribute or Port
LCPLL_REFCLK_DIV
PLLFBDIV[7:0]
LCPLLCLKOUT_RATE
See TX Configurable Driver
SDMDATA[SDMWIDTH + 1:SDMWIDTH]
SDMDATA[SDMWIDTH – 1:0]
SDM_WIDTHSEL
Loop
VCO
Filter
Equation 2-1
N + FractionalDivider
*
M*LCPLLCLKOUT _ RATE
*Modulation
PLLClkout
+ 0. < FractionalPart >
SDM
SDMWIDTH
2
1, 2, 3, 4
16–160 (Integer only)
1'b1: 1 (Full), 1'b0: 2 (Half)
2 (NRZ), 4 (PAM4)
Integer part of fractional divider. (Two's
complement) –2, –1, 0, 1
Fractional part of fractional divider.
24
0 – (2 – 1)
16, 20, 24
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Chapter 2: Shared Features
PLL
LOCKED
PLL
/2
CLKOUT
LCPLLCLKOUT_RATE
X20901-052418
shows how to
Valid Settings
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