Xilinx Virtex UltraScale+ FPGAs User Manual page 116

Table 71: RX Interface Ports (cont'd)
Port
RXUSRCLK
RXUSRCLK2
The following table defines the TX interface attributes.
Table 72: RX Interface Attributes
Attribute
CH[0/1]_RX_PCS_CFG0
Bit Name
RX_DATA_WIDTH
RX_INT_DATA_WIDTH
GEN_RXUSRCLK
CH[0/1]_A_CH_CFG0
Bit Name
RX_FABINT_USRCLK_FLOP
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir Clock Domain
In Clock
In Clock
Type
16-bit
Address
[2:0]
[4:3]
[14]
16-bit
Address
[1]
Description
This port is used to provide a clock for the internal RX
PCS datapath.
This port is used to synchronize the interconnect logic
with the RX interface. This clock must be positive-edge
aligned to RXUSRCLK.
Description
Reserved.
Description
Sets the bit width of the RXDATA port. When FEC is enabled,
RX_DATA_WIDTH must be set to 160:
0x0: 64-bit fabric mode.
0x1: 80-bit fabric mode.
0x2: 128-bit fabric mode.
0x3: 160-bit fabric mode.
0x4: 256-bit fabric mode.
Controls the width of the internal RX PCS datapath. 80-bit
internal datapath must use with 80- or 160-bit fabric width;
128-bit internal datapath must use with 128- or 256-bit
fabric width; 64-bit internal datapath must use with 64 or
128-bit fabric width:
0x0: 64-bit internal datapath mode.
0x1: 80-bit internal datapath mode.
0x2: 128-bit internal datapath mode.
Automatically generates RXUSRCLK from RXUSRCLK2, only
applicable when fabric datapath width is the same as the
internal datapath width:
0x0: Disables automatic RXUSRCLK generation from
RXUSRCLK2.
0x1: Enables automatic RXUSRCLK generation from
RXUSRCLK2.
Reserved.
Description
Determines if port signals are registered again in the
RXUSRCLK domain after being registered in the RXUSRCLK2
domain. This attribute only applies if the RX internal
datapath width is the same as the RX interface width,
otherwise this attribute is ignored. Use the recommended
value from the Wizard.
0x0: Bypass RXUSRCLK flip-flops.
0x1: Enable RXUSRCLK flip-flops.
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Chapter 4: Receiver
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