Table Of Contents - Xilinx Virtex UltraScale+ FPGAs User Manual

Table of Contents

Revision History
Chapter 1: Transceiver and Tool Overview
Introduction to the UltraScale Architecture.............................................................................5
Features........................................................................................................................................ 6
UltraScale+ FPGAs GTM Transceivers Wizard.......................................................................... 9
Simulation.................................................................................................................................. 10
Implementation.........................................................................................................................11
Chapter 2: Shared Features
Reference Clock Input/Output Structure............................................................................... 12
Reference Clock Selection and Distribution...........................................................................14
LCPLL...........................................................................................................................................18
Reset and Initialization............................................................................................................. 23
Power Down...............................................................................................................................45
Loopback.................................................................................................................................... 46
Dynamic Reconfiguration Port................................................................................................ 47
Digital Monitor...........................................................................................................................50
Chapter 3: Transmitter
TX Interface................................................................................................................................ 55
TX FEC......................................................................................................................................... 63
TX Buffer..................................................................................................................................... 66
TX Pattern Generator................................................................................................................ 67
TX Polarity Control.....................................................................................................................71
TX Gray Encoder........................................................................................................................ 71
TX Pre-Coder.............................................................................................................................. 72
TX Fabric Clock Output Control............................................................................................... 73
TX Configurable Driver............................................................................................................. 77
Chapter 4: Receiver
RX Analog Front End................................................................................................................. 85
RX Equalizer............................................................................................................................... 87
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
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