Xilinx Virtex UltraScale+ FPGAs User Manual page 52

Table 27: Digital Monitor Attributes (cont'd)
Attribute
CH[0/1]_RX_APT_CFG14B
Bit Name
FFELOOPSEL
Use Mode
Reading loop values out of Digital Monitor requires a clock on input port
CH0/1_DMONITORCLK, change adaptation loop select through DRP, and monitor output
CH0/1_DMONITOROUT. Set attributes DMON_ENABLE, DMON_SRC, DEMONCON, TESTSEL,
and DFELOOPSEL, or FFELOOPSEL via DRP port to enable the digital monitor and select the
appropriate loop for monitoring. The DRP locations of the attributes are follows.
Channel 0:
• 0x082[0]: DMON_ENABLE
• 0x082[2:1]: DMON_SRC
• 0x033[14:12]: DEMONCON
• 0x03B[15]: TESTSEL
• 0x046[15:12]: DFELOOPSEL
• 0x03f[15:12]: FFELOOPSEL
Channel 1:
• 0x282[0]: DMON_ENABLE
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Type
16-bit Reserved.
Bit Field Description
[15:12] Selector to monitor FFE adaptation loops for channel 0/1.
Value
4'b0001
4'b0010
4'b0011
4'b0100
4'b0101
4'b0110
4'b0111
4'b1000
4'b1001
4'b1010
4'b1011
4'b1100
4'b1101
4'b1110
Chapter 2: Shared Features
Description
Adaptation Loop
FFE tap hm01.
FFE tap hm02.
FFE tap hm03.
FFE tap hm04.
FFE tap hp02.
FFE tap hp03.
FFE tap hp04.
FFE tap hp05.
FFE tap hp06.
FFE tap hp07.
FFE tap hp08.
FFE tap hp09.
FFE tap hp10.
FFE tap hp11.
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