Xilinx Virtex UltraScale+ FPGAs User Manual page 57

TXUSRCLK2 is the main synchronization clock for all signals into the TX side of the GTM
transceiver. Most signals into the TX side of the GTM transceiver are sampled on the positive
edge of TXUSRCLK2. TXUSRCLK2 and TXUSRCLK have a fixed-rate relationship based on the
TX_DATA_WIDTH and TX_INT_DATA_WIDTH settings. The following table shows the
relationship between TXUSRCLK2 and TXUSRCLK per TX_DATA_WIDTH and
TX_INT_DATA_WIDTH values.
Table 29: Relationship between TXUSRCLK2 and TXUSRCLK
Encoding
NRZ
NRZ
PAM4
PAM4
PAM4
PAM4
These rules about the relationships between clocks must be observed for TXUSRCLK and
TXUSRCLK2:
• TXUSRCLK and TXUSRCLK2 must be positive-edge aligned, with as little skew as possible
between them. As a result, low-skew clock resources (BUFG_GTs) must be used to drive
TXUSRCLK and TXUSRCLK2.
• Even though they might run at different frequencies, TXUSRCLK, TXUSRCLK2, and the
transmitter reference clock must have the same oscillator as their source. Thus TXUSRCLK
and TXUSRCLK2 must be multiplied or divided versions of the transmitter reference clock.
Ports and Attributes
The following table defines the TX interface ports.
Table 30: TX Interface Ports
Port
TXDATA[255:0]
TXUSRCLK
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
TX Data Width TX Internal Datapath
64
128
80
160
128
256
Dir Clock Domain
In TXUSRCLK2
In Clock
TXUSRCLK2 Frequency
64
64 F
80
80 F
128
128 F
Description
The bus for transmitting data. The width of this port
is equal to the TX data width selection.
64: TXDATA[63:0].
80: TXDATA[79:0].
128: TXDATA[127:0].
160: TXDATA[159:0].
256: TXDATA[255:0].
This port is used to provide a clock for the internal
TX PCS datapath.
Send Feedback
Chapter 3: Transmitter
F = F
TXUSRCLK2 TXUSRCLK
= F /2
TXUSRCLK2 TXUSRCLK
F = F
TXUSRCLK2 TXUSRCLK
= F /2
TXUSRCLK2 TXUSRCLK
F = F
TXUSRCLK2 TXUSRCLK
= F /2
TXUSRCLK2 TXUSRCLK
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