Xilinx Virtex UltraScale+ FPGAs User Manual page 107

When the RS-FEC is enabled in the receive direction, data received by the GTM PMA and PCS is
passed to the Integrated KP4 RS-FEC. The RS-FEC then aligns and deskews the input lanes
according to the configured mode to reconstruct the transmitted RS codeword stream. The RS-
FEC then performs RS decoding according to the 802.3bj clause 91 specification. The decoded
output data from the Integrated KP4 RS-FEC is then presented on the output of the GTM
transceiver to the fabric.
The Integrated KP4 RS-FEC does not natively perform transcoding, alignment marker removal,
alignment marker mapping, or alignment marker insertion operations in the receive directions. To
support protocols such as 100G Ethernet (IEEE 802.3 clause 91) and 50G Ethernet (IEEE 802.3
clause 134) which require 257b transcoding and alignment marker processing, the GTM Wizard
IP can optionally include soft logic blocks for these functions.
Ports and Attributes
The following table shows the RX FEC-related ports for the GTM dual.
Table 66: RX FEC Ports
Ports
CH[0/1]_RXFECRESET
CH[0/1]_RXDATA[159:0]
CH[0/1]_RXDATASTART
CH[0/1]_RXDATAISAM
CH[0/1]_RXDATAFLAG[3:0]
FECCTRLRX0BITSLIPFS
FECCTRLRX1BITSLIPFS
FECRX0ALIGNED
FECRX1ALIGNED
FECRX0CWINC
FECRX1CWINC
FECRX0CORRCWINC
FECRX1CORRCWINC
FECTRXLN0LOCK
FECTRXLN1LOCK
FECTRXLN2LOCK
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir Clock Domain
In Async
Out CH[0/1]_RXUSRCLK2
Out CH[0/1]_RXUSRCLK2
Out CH[0/1]_RXUSRCLK2
Out CH[0/1]_RXUSRCLK2
In CH0_RXUSRCLK2
In CH1_RXUSRCLK2
Out CH0_RXUSRCLK2
Out CH1_RXUSRCLK2
Out CH0_RXUSRCLK2
Out CH1_RXUSRCLK2
Out CH0_RXUSRCLK2
Out CH1_RXUSRCLK2
Out CH0_RXUSRCLK2
Out CH0_RXUSRCLK2
Out CH1_RXUSRCLK2
Chapter 4: Receiver
Description
Component reset port for RX FEC.
Output RX data. Must use 160-bit interface
when FEC is enabled.
Start of codeword.
Alignment marker flag.
Codeword status flags:
Bit 0: When High, indicates the codeword
input to the decoder has no errors.
Bit 1: When High, indicates the codeword
input to the decoder has errors.
Bit 2: When High, indicates the codeword
output from the decoder has no errors.
Bit 3: When High, indicates the codeword
output from the decoder has errors.
Bitslip control for slice 0.
Bitslip control for slice 1.
Slice 0 alignment status.
Slice 1 alignment status.
Slice 0 codeword count increment.
Slice 1 codeword count increment.
Slice 0 corrected codeword count increment.
Slice 1 corrected codeword count increment.
Lane 0 lock status.
Lane 1 lock status.
Lane 2 lock status.
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