Reference Clock Interface - Xilinx Virtex UltraScale+ FPGAs User Manual

• Meet or exceed the reference clock characteristics as specified in the UltraScale+ device data
sheets.
• Meet or exceed the reference clock characteristics as specified in the standard for which the
GTM transceiver provides physical layer support.
• Fulfill the oscillator vendor's requirement regarding power supply, board layout, and noise
specification.
• Provide a dedicated point-to-point connection between the oscillator and GTM transceiver
Dual clock input pins.
• Keep impedance discontinuities on the differential transmission lines to a minimum
(impedance discontinuities generate jitter).

Reference Clock Interface

LVDS
The following figure shows how an LVDS oscillator is connected to a reference clock input of a
GTM transceiver.
Interfacing an LVDS Oscillator to the GTM Transceiver Reference Clock
Figure 53:
LVDS Oscillator
LVPECL
The following figure shows how an LVPECL oscillator is connected to a reference clock input of a
GTM transceiver.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Chapter 5: Board Design Guidelines
Input
0.01 µF
0.01 µF
Send Feedback
Internal to
UltraScale+ Device
GTM Transceiver
Reference Clock
Input Buffer
X20934-053118
www.xilinx.com
123