Xilinx Virtex UltraScale+ FPGAs User Manual page 70

Table 39: Pattern Generator Attribute
Attribute
CH[0/1]_TX_PCS_CFG1
Bit Name
RXPRBSERR_LOOPBACK
Using TX Pattern Generator
The GTM TX pattern generator works for all supported data widths. However, 80-bit or 160-bit
TX fabric data width in PAM4 mode requires additional steps. Other data widths do not require
any additional steps.
Enable TX Pattern Generator for 80-bit or 160-bit Data Width
1. Using the DRP interface, write the following values to CH[0/1]_TX_PCS_CFG0[4:0] (address
0x083 for CH0, 0x283 for CH1):
a. CH[0/1]_TX_PCS_CFG0[4:0] = 0x12 for 80-bit data width mode.
b. CH[0/1]_TX_PCS_CFG0[4:0] = 0x14 for 160-bit data width mode.
2. Enable the PRBS generator by setting CH[0/1]_TXPRBSPTN to the required value for the
desired pattern.
3. TX PRBS pattern generator is enabled.
:
Note Toggling CH[0/1]_TXPRBSINSERR for one CH[0/1]_TXUSRCLK2 cycle might inject more than one
error into the pattern generator in 80/160 bit mode.
Disable TX Pattern Generator for 80-bit or 160-bit Data Width
1. Disable the PRBS generator by setting CH[0/1]_TXPRBSPTN[3:0] to 4'b0000.
2. Using the DRP interface, write the following values to CH[0/1]_TX_PCS_CFG0[4:0] (address
0x083 for CH0, 0x283 for CH1):
a. CH[0/1]_TX_PCS_CFG0[4:0] = 0x09 for 80-bit data width mode.
b. CH[0/1]_TX_PCS_CFG0[4:0] = 0x0B for 160-bit data width mode.
3. Set CH[0/1]_TXPMARESETMASK = 0x0.
4. Toggle CH[0/1]_GTTXRESET High and Low.
5. Wait for CH[0/1]_TXRESETDONE to toggle High.
6. Set CH[0/1]_TXPMARESETMASK = 0x3.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Type
16-bit Reserved.
Address Description
[7] Setting this attribute to 1'b1 causes the CH[0/1]_RXPRBSERR bit to
be internally looped back to CH[0/1]_TXPRBSINERR of the same
GTM transceiver. This allows synchronous and asynchronous jitter
tolerance testing without worrying about data clock domain
crossing. Setting this attribute to 1'b0 causes
CH[0/1]_TXPRBSINERR to be forced onto the TX PRBS.
Chapter 3: Transmitter
Description
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