Xilinx Virtex UltraScale+ FPGAs User Manual page 74

GTM_DUAL (GTM Transceiver Primitive)
TX PMA
TXP/N
PISO
TX CLKGEN
LCPLL
REFCLK SEL
REFCLK
Distribution
IBUFDS_GTM
MGTREFCLKP
MGTREFCLKN
REFCLK_HROW_CK_SEL
Notes relevant to the figure:
1. CH[0/1]_TXPROGDIVCLK is used as the source of the interconnect logic clock via BUFG_GT.
2. There is only one LCPLL in the GTM_DUAL primitive, which is shared between the TX/RX.
TX Programmable Divider
The TX programmable divider shown in
parallel output clock. By using the transceiver LCPLL, TX programmable divider, and BUFG_GT,
CH[0/1]_TXPROGDIVCLK should be used as a clock source for the interconnect logic.
The following tables show the programmable divider ports and attributes, respectively.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
TX Serial and Parallel Clock Divider
Figure 34:
TX DATA
/32
TX PROG
DIV
Output to
GTM_DUAL
O
ODIV2
Figure 34
TX PCS
Polarity Pre- Gray
Control Coder Encoder
CH[0/1]_TXPROGDIVCLK
Output Clock to BUFG_GT
uses the LCPLL output clock to generate a
Send Feedback
Chapter 3: Transmitter
TX DATA from
Upstream PCS Blocks
TX FIFO
CH[0/1]_TXUSRCLK
X20915-110218
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