Xilinx Virtex UltraScale+ FPGAs User Manual page 115

RXUSRCLK2 is the main synchronization clock for all signals into the RX side of the GTM
transceiver. Most signals into the RX side of the GTM transceiver are sampled on the positive
edge of RXUSRCLK2. RXUSRCLK2 and RXUSRCLK have a fixed-rate relationship based on the
RX_DATA_WIDTH and RX_INT_DATA_WIDTH settings. The following table shows the
relationship between RXUSRCLK2 and RXUSRCLK per the RX_DATA_WIDTH and
RX_INT_DATA_WIDTH values.
Table 70: RXUSRCLK2 Frequency Relationship to RXUSRCLK
Encoding
NRZ
PAM4
These rules about the relationships between clocks must be observed for RXUSRCLK and
RXUSRCLK2:
• RXUSRCLK and RXUSRCLK2 must be positive-edge aligned, with as little skew as possible
between them. As a result, low-skew clock resources (BUFG_GTs) must be used to drive
RXUSRCLK and RXUSRCLK2.
• If the channel is configured so that the same oscillator drives the reference clock for the
transmitter and the receiver, TXPROGDIVCLK can be used to drive RXUSRCLK and
RXUSRCLK2 in the same way that they are used to drive TXUSRCLK and TXUSRCLK2.
• If separate oscillators are driving the reference clocks for the transmitter and receiver on the
channel, RXUSRCLK and RXUSRCLK2 must be driven by RXPROGDIVCLK.
Ports and Attributes
The following table defines the TX interface ports.
Table 71: RX Interface Ports
Port
RXDATA[255:0]
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
RX Internal
RX Data Width
Datapath
64
128
80
160
128
256
Dir Clock Domain
Out RXUSRCLK2
RXUSRCLK2 Frequency
64
64
80
80
128
128
The bus for receiving data. The width of this port is
equal to RX data width selection. RX data width
selection:
64: RXDATA[63:0]
80: RXDATA[79:0]
128: RXDATA[127:0]
160: RXDATA[159:0]
256: RXDATA[255:0]
Send Feedback
Chapter 4: Receiver
F = F
RXUSRCLK2 RXUSRCLK
F = F /2
RXUSRCLK2 RXUSRCLK
F = F
RXUSRCLK2 RXUSRCLK
F = F /2
RXUSRCLK2 RXUSRCLK
F = F
RXUSRCLK2 RXUSRCLK
F = F /2
RXUSRCLK2 RXUSRCLK
Description
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