Gtm Transceiver Reference Clock Checklist - Xilinx Virtex UltraScale+ FPGAs User Manual

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The following figure illustrates the internal details of the IBUFDS. The dedicated differential
reference clock input pair MGTREFCLKP/MGTREFCLKN is internally terminated with 100Ω
differential impedance. The common mode voltage of this differential reference clock input pair is
4/5 of MGTAVCC, or nominal 0.8V for UltraScale FPGAs. The common mode voltage for
UltraScale+ FPGAs is MGTAVCC, or nominal 0.9V. See the UltraScale and UltraScale+ device
data sheets (see
MGTREFCLKP
MGTREFCLKN

GTM Transceiver Reference Clock Checklist

These criteria must be met when choosing an oscillator for a design with GTM transceivers:
• Provide AC coupling between the oscillator output pins and the dedicated GTM transceiver
DUAL clock input pins.
• Ensure that the differential voltage swing of the reference clock is the range as specified in the
UltraScale+ device data sheets (see
is 250 mV–2000 mV and the nominal value is 1200 mV).
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Figure 51:
T
FCLK
http:/ /www.xilinx.com/documentation) for exact specifications.
GTM Transceiver Board Design Guidelines
Figure 52:
50Ω
UltraScale+ FPGAs:
MGTAVCC
50Ω
http:/
Chapter 5: Board Design Guidelines
Rise and Fall Times
T
RCLK
REFCLK
/www.xilinx.com/documentation). The nominal range
Send Feedback
X20933-053118
to GTM Transceiver
Dedicated
Clock
Routing
X21023-060718
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