Xilinx Virtex UltraScale+ FPGAs User Manual page 81

Table 46: TX Configurable Driver Ports (cont'd)
Port
CH[0/1]_TXEMPPRE2[3:0]
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Clock
Dir
Domain
Input Async Transmitter pre-cursor 2 TX pre-emphasis control for channel 0.
The default is user specified. All listed values (dB) are typical
[4:0]
4'b0000
4'b0001
4'b0010
4'b0011
4'b0100
4'b0101
4'b0110
4'b0111
4'b1000
4'b1001
4'b1010
4'b1011
Notes:
1. The peak-to-peak differential voltage is defined when
CH[0/1]_TXEMPPRE = 5'b00000, and CH[0/1]_TXEMPPOST
= 4'b0000. Emphasis = 20log10(V
20log10(V
Chapter 3: Transmitter
Description
dB (PAM4) dB (NRZ)
0.0 0.0
–0.3 –0.2
–0.7 –0.5
–1.1 –0.7
–1.5 –0.9
–1.9 –1.2
–2.3 –1.5
–2.7 –1.7
N/A –2.0
N/A –2.3
N/A –2.6
N/A –2.9
/V
high low
/V )|.
low high
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Coefficient
Units
0
1
2
3
4
5
6
7
8
9
10
11
) = |
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