Xilinx Virtex UltraScale+ FPGAs User Manual page 97

Table 55: RX Programmable Divider Attribute (cont'd)
Attribute
RX_PROGDIV_FBDIV
Ports and Attributes
The following table defines the ports required for TX fabric clock output control.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Type
[7:2] This attribute is the main RX programmable divider
selector.
When the following settings are set:
RX_PROGDIV_SEL_DIV66 = 1'b0
RX_PROGDIV_SEL_DIV5 = 1'b1
RX_PROGDIV_SELFR = 1'b1 (or 1'b0)
Valid RX programmable divider ratios are:
6'b011000: 4 (8)
6'b111000: 5 (10)
6'b000000: 8 (16)
6'b100000: 10 (20)
6'b000001: 12 (24)
6'b100001: 15 (30)
6'b000010: 16 (32)
6'b100010: 20 (40)
6'b000101: 24 (48)
6'b100011: 25 (50)
6'b100101: 30 (60)
6'b000110: 32 (64)
6'b100110: 40 (80)
6'b001101: 48 (96)
6'b100111: 50 (100)
6'b101101: 60 (120)
6'b001110: 64 (128)
6'b001111: 80 (160)
6'b101111: 100 (200)
When the following settings are set:
RX_PROGDIV_SEL_DIV66 = 1'b1
RX_PROGDIV_SEL_DIV5 = 1'b0
RX_PROGDIV_SELFR = 1'b1 (or 1'b0)
Valid RX programmable divider ratios are:
6'b011000: 16.5 (33)
6'b000000: 33 (66)
6'b000010: 66 (132)
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Chapter 4: Receiver
Description
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