Xilinx Virtex UltraScale+ FPGAs User Manual page 21

Ports and Attributes
The following tables define the LCPLL ports and attributes, respectively.
Table 9: LCPLL Ports
Port
GTGREFCLK2PLL
PLLFBCLKLOST
PLLFBDIV[7:0]
PLLLOCK
PLLMONCLK
PLLPD
PLLREFCLKLOST
PLLREFCLKMONITOR
PLLRESET
PLLRESETBYPASSMODE
PLLRESETDONE
PLLRESETMASK[1:0]
PLLRSVDIN[15:0]
PLLRSVDOUT
BGBYPASSB
BGMONITORENB
BGPDB
BGRCALOVRD[4:0]
BGRCALOVRDENB
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Clock
Direction
Domain
In Clock Reference clock generated by the internal interconnect
logic. This input is reserved for internal testing purposes.
Out PLLMONCLK A High on this signal indicates the feedback clock from the
LCPLL feedback divider to the phase frequency detector of
the LCPLL is lost
In Async PLL feedback divider selection. Actual feedback divider value
is PLLFBDIV + 2. Valid values are from 14–158. (Actual divider
values are 160–160.)
Out Async This active-High LCPLL frequency lock signal indicates that
the LCPLL frequency is within a predetermined tolerance.
The transceiver and its clock outputs are not reliable until
this condition is met.
In Clock Stable reference clock for the detection of the feedback and
reference clock signals to the LCPLL. The input reference
clock to the LCPLL or any output clock generated from the
LCPLL must not be used to drive this clock. This clock is
required only when using the PLLFBCLKLOST and
PLLREFCLKLOST ports. It does not affect the LCPLL lock
detection, reset, and power-down functions.
In Async An active-High signal powers down the LCPLL.
Out PLLMONCLK A High on this signal indicates the reference clock to the
phase frequency detector of the LCPLL is lost.
Out Clock PLL reference clock selection multiplexer output.
In Async This port is driven High and then deasserted to start the
LCPLL reset.
In Async Reserved. Tied Low.
Out cfg_mclk Status signal that indicates when the PLL reset sequence is
complete.
In Async Bit 0 enables bit mask for PLL reset. Bit 1 enables bit mask
for PLL SDM reset.
In Reserved Reserved. This port must be set to 0x0000.
Out Async Reserved.
In Async Reserved. This port must be set to 1'b1. Do not modify this
value.
In Async Reserved. This port must be set to 1'b1. Do not modify this
value.
In Async Reserved. This port must be set to 1'b1. Do not modify this
value.
In Async Reserved. This port must be set to 5'b11111. Do not modify
this value.
In Async Reserved. This port must be set to 1'b1. Do not modify this
value.
Chapter 2: Shared Features
Description
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