Xilinx Virtex UltraScale+ FPGAs User Manual page 62

Multiple Lanes—TXPROGDIVCLK Drives TXUSRCLK and TXUSRCLK2 (128-Bit,
Figure 29:
UltraScale
Devices GTM
Transceiver
UltraScale
Devices GTM
Transceiver
Notes relevant to the figure:
1. For details about placement constraints and restrictions on clocking resources (BUFG_GT,
BUFG_GT_SYNC, etc.), refer to the UltraScale Architecture Clocking Resources User Guide
(UG572).
2. F = F
TXUSRCLK2
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
160-Bit, or 256-Bit Mode)
TXPROGDIVCLK
TXUSRCLK 2
TXUSRCLK2 2
TXDATA (TX data width = 128/160/256 bits)
TXUSRCLK 2
2
TXUSRCLK2
TXDATA (TX data width = 128/160/256 bits)
/2.
TXUSRCLK
1
BUFG_GT
÷2
BUFG_GT 1
÷1
Design in UltraScale
Architecture
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Chapter 3: Transmitter
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