7.5 Transfer Mode
7.5.1 Single transfer mode
In single transfer mode, the DMAC releases the bus at each byte/halfword/word transfer. If there is a
subsequent DMA transfer request, transfer is performed again once. This operation continues until a
terminal count occurs.
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the
higher priority DMA request always takes precedence. However, if a lower priority DMA transfer request
is generated within one clock after the end of a single transfer, even if the previous higher priority DMA
transfer request signal stays active, this request is not prioritized and the next DMA transfer after the
bus is released for the CPU is a transfer based on the newly generated, lower priority DMA transfer
request.
Figure 7-16, "Single Transfer Example 1," on page 187 shows a DMAC transfer in single transfer mode.
In this example the DMA channel 3 is used for a single transfer.
DMA Transfer
Request CH3
CPU
CPU
Figure 7-17, "Single Transfer Example 2," on page 187 shows DMAC transfers in single transfer mode
in which a higher priority DMA transfer request is generated. DMA channels 0 to 2 are used for a block
transfer and channel 3 is used for a single transfer.
DMA Transfer
Request CH0
DMA Transfer
Request CH1
DMA Transfer
Request CH2
DMA Transfer
Request CH3
CPU
CPU
Note: The bus is always released
Chapter 7 DMA Functions (DMA Controller)
Figure 7-16: Single Transfer Example 1
Note
Note
DMA3 CPU DMA3
CPU
DMA3
Figure 7-17: Single Transfer Example 2
Note
CPU DMA3 CPU
DMA0
DMA0
DMA channel 0
terminal count
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Note
CPU
CPU
CPU
CPU
CPU
Note
Note
CPU DMA1
DMA1
CPU
DMA channel 1
terminal count
Note
CPU
DMA3
CPU DMA3 CPU
DMA chan nel 3 terminal count
Note
DMA2
DMA2 CPU DMA3
DMA channel 2
terminal count
CPU
CPU
CPU DMA3
DMA channel 3
terminal count
187