Power Save Status; Table 7-22: Power Save Status And Local Bus Memory Access Relative To Power Save Mode; Figure 7-23: Power Save Status And Local Bus Memory Access Relative To Power Save Mode; Vancouver Design Center - Epson S1D13505 Technical Manual

Embedded ramdac lcd/crt controller
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7.4.2 Power Save Status

Power Save
Power Save Status Bit
Memory Access

Figure 7-23: Power Save Status and Local Bus Memory Access Relative to Power Save Mode

Note

Table 7-22: Power Save Status and Local Bus Memory Access Relative to Power Save Mode

Symbol
Power Save initiated to rising edge of Power Save Status and the
t1
last time memory access by the local bus may be performed.
t2
Power Save deactivated to falling edge of Power Save Status
Falling edge of Power Save Status to the earliest time the local bus
t3
may perform a memory access
Note
Hardware Functional Specification
Issue Date: 01/02/02
t1
allowed
Power Save can be initiated through either the SUSPEND# pin or Software Suspend Enable Bit.
Parameter
It is recommended that memory access not be performed after a Power Save Mode has been
initiated.
t2
t3
not allowed
Min
129
allowed
Max
Units
130
Frames
12
MCLK
8
MCLK
S1D13505
X23A-A-001-14
Page 75

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