Data Bus (Data Memory) Control; Data Bus Status; High-Impedance Control - Epson S1C63000 Core Cpu Manual

3.3 Data Bus (Data Memory) Control

3.3.1 Data bus status

The S1C63000 output the data bus status in each bus cycle externally on the DBS0 and DBS1 signals as a
2-bit status. The peripheral circuits perform the direction control of the bus driver and other controls with
these signals. The data bus statuses indicated by the DBS0 and DBS1 are as shown in Table 3.3.1.1.

3.3.2 High-impedance control

The data bus goes to a high-impedance during an execution cycle ( ) that accesses only the internal
registers in the CPU. During the bus cycle period, both the read signal RD and write signal WR are fixed
at a high level and a dummy address is output on the address bus.
Data is output on the data bus only when the stack pointer SP1 is accessed because a data transfer is
performed between the queue register and the data memory. In this case, the data bus status becomes a
memory write or a memory read depending on the instruction that accesses the SP1.
S1C63000 CORE CPU MANUAL
Table 3.3.1.1 Data bus status
DBS1 DBS0
0 0
0 1
1 0
1 1
T1
CLK
PK
PL
DA00–DA15
WR
RD
D0–D3
DBS1
DBS0
Fig. 3.3.2.1 Bus cycle during accessing internal register
State
High impedance
Interrupt vector read
Memory write
Memory read
T2 T3 T4
Dummy address
Bus cycle
EPSON
CHAPTER 3: CPU OPERATION
23