Samsung S5PC100 User Manual page 1709

PCM AUDIO INTERFACE
6.2 PCM CLK CONTROL REGISTER
PCM_0_CLKCTL, R/W, Address = 0xF240_0004
PCM_1_CLKCTL, R/W, Address = 0xF250_0004
The bit definitions for the PCM_n_CTL Control Register are described below:
PCM_n_CLKCTL
Reserved
CTL_SERCLK_EN
CTL_SERCLK_SEL
SCLK_DIV
SYNC_DIV
6.3 THE PCM TX FIFO REGISTER
PCM_0_TXFIFO, R/W, Address = 0xF240_0008
PCM_1_TXFIFO, R/W, Address = 0xF250_0008
The bit definitions for the PCM_n_TXFIFO Register are described below:
PCM_n_TXFIFO
Reserved
TXFIFO_DVALID
TXFIFO_DATA
10.5-8
Bit
[31:20] Reserved
[19] Enables the serial clock division logic.
Must be HIGH for the PCM to operate
[18] Selects the source of the serial clock
0 - SCLK_AUDIO
1 - PCLK
[17:9] Controls the divider used to create the PCMSCLK based on
the PCMCODEC_CLK
Final clock is source_clk / 2*(sclk_div+1)
[8:0] Controls the frequency of the PCMSYNC signal based on
the PCMSCLK.
Bit
[31:17] Reserved
[16] TXFIFO data is valid
Write: Not valid
Read: TXFIFO read data valid
1 = Valid
0 = Invalid (probably read an empty fifo)
[15:0] TXFIFO DATA
Write: TXFIFO_DATA is written into the TXFIFO
Read: TXFIFO is read using the APB interface
NOTE: reading the TXFIFO is meant to support
debugging.
Online the TXFIFO is read by the PCM serial shift engine,
not the APB
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Reset Value
0
0
0
000
000
Reset Value
0
1
0