Samsung S5PC100 User Manual page 1689

AC97 CONTROLLER
Slot 1: Command Address Port
In slot 1, it communicates control register address and write/ read command information to the AC97 controller. If
software accesses the primary CODEC, the hardware configures the frame as follows:
•
In slot 0, the valid bit for 1 and 2 slots are set.
•
In slot 1, bit 19 is set (read) or clear (write). Bits 18-12 (of slot 1) are configured to specify the index to the
CODEC register. Others are filled with 0's (reserved).
•
In slot 2, it configured with the data which is for writing because of output frame.
Slot 2: Command Data Port
In slot 2, this is the write data with 16-bit resolution ([19:4] is valid data)
Slot 3: PCM Playback Left channel
Slot 3 which is audio output frame is the composite digital audio left stream. If a sample has a resolution that is
less than 16 bits, the AC97 controller fills all training non-valid bit positions in the slot with zeroes.
Slot 4: PCM Playback Right channel
Slot 4 which is audio output frame is the composite digital audio right stream. If a sample has a resolution that is
less than 16 bits, the AC97 controller fills all training non-valid bit positions in the slot with zeroes.
SYNC
AC '97 samples SYNC assertion here
AC '97 Controller samples first SDATA_OUT bit of frame here
BIT_CLK
Valid
SDATA_OUT
Frame
END of previous Audio Frame
10.4-6
Tag Phase
Slot(1) Slot(2) Slot(12)
Figure 10.4-5 AC-link Output Frame
48KHz
12.288MHz
"0" ID1 ID0 19
START of Data phase
Slot# 1
S5PC100 USER'S MANUAL (REV1.0)
Data Phase
0 19
END of Data Frame
0
Slot# 12