Samsung S5PC100 User Manual page 1678

I2S CONTROLLER(2CH)
I2SCON
LRI
FTXEMPT
FRXEMPT
FTXFULL
FRXFULL
TXDMAPAUSE
RXDMAPAUSE
TXCHPAUSE
RXCHPAUSE
TXDMACTIVE
10.3-14
Bit
[11] Left/ Right channel clock indication. Note that LRI meaning
is dependent on the value of LRP bit of I2SMOD register.
0 = Left (If LRP bit is low) or right (If LRP bit is high)
1= Right (If LRP bit is low) or left (If LRP bit is high)
[10] Tx FIFO empty status indication.
0 = FIFO is not empty (ready for transmit data to channel)
1 = FIFO is empty (not ready for transmit data to channel)
[9] Rx FIFO empty status indication.
0 = FIFO is not empty
1 = FIFO is empty
[8] Tx FIFO full status indication.
0 = FIFO is not full
1 = FIFO is full
[7] Rx FIFO full status indication.
0 = FIFO is not full (ready to receive data from channel)
1= FIFO is full (not ready to receive data from channel)
[6] Tx DMA operation pause command.
Note: If this bit is activated at any time, the DMA request
halts after current on-going DMA transfer is complete.
0 = No pause DMA operation
1= Pause DMA operation
[5] Rx DMA operation pause command.
Note: If this bit is activated at any time, the DMA request
halts after current on-going DMA transfer is complete.
0 = No pause DMA operation
1 = Pause DMA operation
[4] Tx channel operation pause command.
Note: If this bit is activated at any time, the channel
operation halts after left-right channel data transfer is
complete.
0 = No pause operation
1 = Pause operation
[3] Rx channel operation pause command.
Note: If this bit is activated at any time, the channel
operation halts after left-right channel data transfer is
complete.
0 = No pause operation
1 = Pause operation
[2] Tx DMA active (start DMA request).
Note: If this bit is set from high to low, the DMA operation
is forced to stop immediately.
0 = Inactive, 1 = Active
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W
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R/W
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R/W
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Reset
Value