Handling More Than 64 Interrupts; Intel486™ Processor Lan Controller Interface; Intel486™ Processor Lan Controller Interface; 82596Ca Coprocessor - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
The timing interface resembles that used for single devices. During the first interrupt acknowl-
edge cycle, all the 82C59A devices freeze the states of their interrupt request inputs. The master
controller outputs the cascaded address to select the slave controller that is generating the request
with the highest priority. During the second interrupt acknowledge cycle, the selected slave con-
troller outputs an interrupt vector to the Intel486 processor.
7.5.2.3

Handling More than 64 Interrupts

If an Intel486 processor-based system requires more than 64 interrupt request lines, a third
82C59A device level in polled mode is added to the configuration shown in
the third-level interrupt controller receives an interrupt, it drives an interrupt request input to the
slave controller on the second level. The second-level slave controller then sends an interrupt re-
quest to the master controller, which in turn interrupts the processor. The slave controller then
returns a service routine vector to the Intel486 processor. The service routine must include com-
mands to poll the third level to determine the source of the interrupt request.
The additional hardware required to implement this configuration includes additional 82C59A
devices and the chip-select logic.
7.6 Intel486™ PROCESSOR LAN CONTROLLER INTERFACE
This section describes two LAN interface solutions using Intel controllers: the 82596CA copro-
cessor and the PCI-compliant 82557 controller for fast Ethernet networks.
7.6.1

82596CA Coprocessor

The 82596CA coprocessor (hereafter referred to generically as the 82596 coprocessor) is a 32-bit
multitasking LAN coprocessor which implements the carrier-sense, multiple-access and colli-
sion-detect (CSMA/CD) link access protocol. The coprocessor supports a wide variety of net-
works. It executes high-level commands, and it performs command chaining and inter-processor
communication via memory shared with the Intel486 processor. This relieves the processor of all
time-critical local-network control functions.
The coprocessor's features include:
•
Complete CSMA/CD Functions
— Complete media access control (MAC) functions
— High-level command interface
— Manchester encoding or NRZ encoding and decoding
— IEEE 802.3 or CCITT HDLC frame delimiting
7-38
Figure 7-19. Once