Lpdac0 Data Out Register; Lpdac0 Switch Control Register - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262
Bits Bit Name Settings
2 SW2
1 SW1
0 SW0

LPDAC0 DATA OUT REGISTER

Address: 0x400C2120, Reset: 0x00000000, Name: LPDACDAT0
Table 113. Bit Descriptions for LPDACDAT0
Bits Bit Name Settings
[31:18] Reserved
[17:12] DACIN6
111111
[11:0] DACIN12
0xFFF

LPDAC0 SWITCH CONTROL REGISTER

Address: 0x400C2124, Reset: 0x00000000, Name: LPDACSW0
Table 114. Bit Descriptions for LPDACSW0
Bits Bit Name Settings
[31:6] Reserved
5 LPMODEDIS
4 SW4
3 SW3
2 SW2
1 SW1
0 SW0
Description
SW2 Switch Control Active High.
0 Open switch.
1 Close switch.
SW1 Switch Control Active High.
0 Open switch.
1 Close switch.
SW0 Switch Control Active High.
0 Open switch.
1 Close switch.
Description
Reserved.
6-Bit Value, 1 LSB = 34.375 mV. A low power DAC0 6-bit output data register value
between 0 and 0x3F is expected to set 6-bit output voltage.
0 0.2 V.
2.366 V.
12-Bit Value, 1 LSB = 537 μV. A low power DAC0 12-bit output data register value
between 0 and 0xFFF is expected to set 12-bit output voltage.
0 0.2 V.
2.4 V.
Description
Reserved.
Switch Control. Controls switches connected to the output of low power DAC0.
0 Switches connected to output of low power DAC configured via LPDACCON0,
Bit 5. Default.
1 Overrides LPDACCON0, Bit 5. Switches connected to the low power DAC0
output are controlled via LPDACSW0, Bits[4:0].
LPDAC0 SW4 Control.
0 Disconnect direct connection of VBIAS0 DAC output to positive input of low
power Amplifier 0. Default.
1 Connect VBIAS0 DAC output directly to positive input of low power Amplifier 0.
LPDAC0 SW3 Control.
0 Disconnect VBIAS0 DAC output from low-pass filter and VBIAS0 pin.
1 Connect VBIAS0 DAC output to the low-pass filter and VBIAS0 pin. Default.
LPDAC0 SW2 Control.
0 Disconnect direct connection of VZERO0 DAC output to low power TIA0 positive
input. Default.
1 Connect VZERO0 DAC output directly to low power TIA0 positive input.
LPDAC0 SW1 Control.
0 Disconnect VZERO0 DAC output from the low-pass filter and VZERO0 pin.
1 Connect VZERO0 DAC output to the low-pass filter and VZERO0 pin. Default.
LPDAC0 SW0 Control.
0 Disconnect VZERO0 DAC output from high speed TIA positive input. Default.
1 Connect VZERO0 DAC output to the high speed TIA positive input.
ADuCM355
Rev. B | Page 98 of 312
Hardware Reference Manual
Reset Access
0x0 R/W
0x0 R/W
0x0 R/W
Reset Access
0x0 R
0x0 R/W
0x0 R/W
Reset Access
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
R/W
0x0
0x0 R/W
0x0 R/W