Crc Data Transfer; Crc Interrupts And Exceptions; Crc Programming Model - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262
Reset and Hibernate Modes
The CRC configuration bits are retained, except for the block enable bit (CTL, Bit 0). The block must be enabled again after exiting
hibernate mode. The CRC polynomial and CRC result registers are retained after exiting hibernate mode. See Table 402 for details on the
CRC registers after a reset and in hibernate mode.
Table 402. Reset and Hibernate by Register
Register Reset
CTL 0x10000000
POLY 0x04C11DB7
IPDATA 0x0
Result 0x0

CRC DATA TRANSFER

The data stream can be written to the block using the DMA controller or by using the MCU directly.

CRC INTERRUPTS AND EXCEPTIONS

The DMA channel generates an interrupt upon completion of data transfer to the CRC block.

CRC PROGRAMMING MODEL

The CRC block is provided to calculate the CRC signature over a block of data in the background while the core performs other tasks.
The CRC block supports two modes of CRC calculation: core access and DMA access.
Core Access Steps
To access the core, take the following steps:
1. Program the POLY register with the required polynomial justified, as detailed in the Polynomial section.
2. Program the result register with the initial seed. The seed must be justified and written to the result register, as detailed in the
Polynomial section.
3. Enable accelerator function by writing to the CTL register. Note that the following steps require a single write to the CTL register:
a. Set the EN bit high.
b. Modify the W16SWP, BYTMIRR, and BITMIRR bits in the CTL register, which configure the application with different
mirroring options. For more information, see the Mirroring Options section.
c. Set or reset the LSBFIRST bit to indicate whether to use LSB first or MSB first in CRC calculation.
The core can start sending data to the CRC block by writing into the IPDATA register. The CRC accelerator continues to calculate
the CRC as long as data is written to the IPDATA register. It is the responsibility of the application to count the number of words
written to the CRC block. After all the words are written, the application can read the result register.
4. Read the result register. This register contains the x-bit result in x MSB bits for MSB first and in x LSB bits for LSB first CRC calculation.
5. Calculate CRC on the next data block. To calculate the CRC on the next block of data, repeat Step 1 to Step 4.
6. Disable the CRC accelerator block by clearing the EN bit in CTL to ensure that the block is in a low power state.
DMA Access Steps
The CRC accelerator block supports software DMA. To access the DMA, take the following steps:
1. Program the POLY register with the required polynomial left justified, as shown in the Polynomial section.
2. Program the result register with an initial seed value. The seed must be justified and written to the result register, as detailed in the
Polynomial section.
3. Enable accelerator function by writing to the CTL register. Note that the following steps require a single write to the CTL register:
a. Set the EN bit high.
b. Modify the W16SWP, BYTMIRR, and BITMIRR bits in the CTL register, which configure the application with different
mirroring options. For more information, see the Mirroring Options section.
c. Set or reset the LSBFIRST bit to indicate LSB first or MSB first CRC calculation.
The DMA can start sending CRC data by writing to the IPDATA register. The CRC accelerator block continues to calculate the CRC
as long as the data is written to IPDATA.
4. Set up the DMA channels using the required parameters: DST_END_PTR is the IPDATA register address, data size is the word,
destination no increment is the channel used. For more information about programming the DMA, see the DMA Controller
section. A DMA_DONE interrupt signal of the DMA channel indicates the completion of data transfer to the CRC block.
5. Repeat Step 1 to Step 4 until all the data has been sent to the accelerator block.
ADuCM355
Hibernate
Apart from EN, all other bits retained
Retained
Not retained
Retained
Rev. B | Page 306 of 312
Hardware Reference Manual