Clear Interrupt Register; 16-Bit Load Value, Asynchronous Register; 16-Bit Timer Value, Asynchronous Register - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual
Bits Bit Name Settings
2 UP
[1:0] PRE
00
01
10
11

CLEAR INTERRUPT REGISTER

Address: 0x400C0D0C, Reset: 0x0000, Name: CLRI0
Table 356. Bit Descriptions for CLRI0
Bits Bit Name Settings
[15:2] Reserved
1 CAP
0 TMOUT

16-BIT LOAD VALUE, ASYNCHRONOUS REGISTER

Address: 0x400C0D14, Reset: 0x0000, Name: ALD0
Only use when a synchronous clock source is selected (CON0, Bits[6:5] = 00).
Table 357. Bit Descriptions for ALD0
Bits Bit Name Settings
[15:0] ALOAD

16-BIT TIMER VALUE, ASYNCHRONOUS REGISTER

Address: 0x400C0D18, Reset: 0x0000, Name: AVAL0
Only use when a synchronous clock source is selected (CON0, Bits[6:5] = 00).
Table 358. Bit Descriptions for AVAL0
Bits Bit Name Settings
[15:0] AVAL
Description
Count Up. Used to control whether the timer increments (counts up) or decrements
(counts down) the up or down counter.
1 Timer is set to count up.
0 Timer is set to count down. Default.
Prescaler. Controls the prescaler division factor applied to the selected clock of the timer.
Source clock/1 or source clock/4. When CON0, Bit 15 is set, source is source clock/1.
When cleared, the source is source clock/4.
Source clock/16.
Source clock/64.
Source clock/256.
Description
Reserved.
Clear Captured Event Interrupt. This bit is used to clear a capture event interrupt.
1 Clear the capture event interrupt.
0 No effect.
Clear Timeout Interrupt. This bit is used to clear a timeout interrupt.
1 Clears the timeout interrupt.
0 No effect.
Description
Load Value, Asynchronous. The up or down counter is periodically loaded with this value if
periodic mode is selected (CON0, Bit 3 = 1). Writing ALOAD takes advantage of having
the timer run on PCLK by bypassing clock synchronization logic that is otherwise required.
Description
Counter Value. Reflects the current up or down counter value. Reading AVAL takes
advantage of having the timer run on PCLK by bypassing clock synchronization logic
that is otherwise required.
Rev. B | Page 277 of 312
UG-1262
Reset Access
0x0 R/W
0x2 R/W
Reset Access
0x0 R
0x0 W1C
0x0 W1C
Reset Access
0x0 R/W
Reset Access
0x0 R