Dma Controller; Dma Features; Dma Overview; Dma Analog Die - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual

DMA CONTROLLER

The DMA controller is used to perform data transfer tasks between peripherals and memory locations to offload these tasks from the
microcontroller unit (MCU). Data can be moved quickly by the DMA without CPU actions, keeping the CPU free for other operations.

DMA FEATURES

The ADuCM355 provides dedicated and independent DMA channels. There are two programmable priority levels for each DMA
channel. Each priority level arbitrates using a fixed priority that is determined by the DMA channel number. Channels with lower
numbers have higher priority. For example, SPI0 transmit has the highest priority, and the next highest priority is the SPI0 receive.
Each DMA channel can access a primary or alternate channel control structure. Multiple DMA transfer types are supported, such as the
following:

Memory to memory.

Memory to peripheral.

Peripheral to memory.

DMA OVERVIEW

The DMA controller has 20 channels in total. The 20 channels are dedicated to managing DMA requests from specific peripherals.
Channels are assigned, as shown in Table 188.
Table 188. DMA Channel Assignment
Channel Number
0
1
2, 3, 6, 7, 13, 14
4
5
8
9
10
11
12
15
16
17
18 to 23

DMA ANALOG DIE

The ADC on the AFE die can be connected to the DMA controller. An eight-word FIFO is provided to buffer. The output of the FIFO is
the DMA controller. The user can select from the following inputs:

ADC sinc3 result (16 bits)

DFT result, real first followed by imaginary part (18 bits for each device)

ADC sinc2 and low-pass filter result (16 bits)

ADC mean result (16 bits)
AFE Die Data FIFO
DMA Channel 17 is associated with the AFE die data FIFO. To enable this die, write 1 to FIFOCON, Bit 12. When the FIFO is enabled
(FIFOCON, Bit 11 = 1) and FIFOCON, Bit 12 = 1, the FIFO issues a DMA request any time the FIFO is not empty.
Peripheral Description
SPI1 transmit
SPI1 receive
Reserved
SPI0 transmit
SPI0 receive
UART0 transmit
UART0 receive
I2C slave transmit
I2C slave receive
I2C master
Flash
Software DMA
AFE die ADC
Software DMA
Rev. B | Page 163 of 312
UG-1262