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2.16.3 Wait Mode Set-Up
Settings and operation for entering wait mode are described here.
Operation
(1) Enables the interrupt used for returning from wait mode.
(2) Sets the interrupt enable flag (I flag) to "1".
(3) Clears the protection and changes the content of the system clock control register.
(4) Executes the WAIT instruction.
( 1 ) S e t t i n g i n t e r r u p t t o c a n c e l w a i t m o d e
b 7
Disable the interrupt not to be used for cancelling wait mode.
(2) Interrupt enable flag (I flag)
( 3 ) C a n c e l i n g p r o t e c t
b7
( 3 ) C o n t r o l o f C P U c l o c k
b 7
0 0 0 0
N o t e 1 : W h e n s w i t c h i n g t h e s y s t e m c l o c k , i t i s n e c e s s a r y t o w a i t f o r t h e o s c i l l a t i o n t o s t a b i l i z e .
N o t e 2 : S e t t h e W A I T p e r i p h e r a l f u n c t i o n c l o c k s t o p b i t t o " 0 " w h e n t h e s y s t e m c l o c k s e l e c t b i t i s " 1 " .
( 4 ) W A I T i n s t r u c t i o n
I n s e r t J M P . B i n s t r u c t i o n b e f o r e t h e W A I T i n s t r u c t i o n a n d a t l e a s t f o u r N O P s a f t e r t h e W A I T i n s t r u c t i o n .
Figure 2.16.6. Example of wait mode set-up
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
I n t e r r u p t c o n t r o l r e g i s t e r
K U P I C
[ A d d r e s s 0 0 4 1
]
1 6
S i R I C ( i = 0 , 2 , 3 )
[ A d d r e s s 0 0 4 A
, 0 0 4 2
1 6
S 1 3 B C N I C
[ A d d r e s s 0 0 4 3
]
1 6
T A i I C ( i = 0 t o 4 )
[ A d d r e s s 0 0 5 4
, 0 0 4 5
1 6
E P 0 I C
[ A d d r e s s 0 0 4 6
]
1 6
A D I C
[ A d d r e s s 0 0 4 B
]
1 6
S i T I C ( i = 0 t o 3 )
[ A d d r e s s 0 0 5 3
, 0 0 5 1
1 6
S U S P I C
[ A d d r e s s 0 0 5 6
]
1 6
R S M I C
[ A d d r e s s 0 0 5 8
]
1 6
S O F I C
[ A d d r e s s 0 0 5 B
]
1 6
V B D I C
[ A d d r e s s 0 0 5 C
]
1 6
U S B F I C
[ A d d r e s s 0 0 5 D
]
1 6
b 0
I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t
Make sure that the interrupt priority
level of the interrupt which is used
to cancel the wait mode is higher
than the processor interrupt priority
(IPL) of the routine where the
WAIT instruction is executed.
"1"
b0
P r o t e c t r e g i s t e r [ A d d r e s s 0 0 0 A
0
1
P R C R
Enables writing to system clock control registers 0 and 1(addresses 0006
frequency synthesizer registers (addresses 03DB
1 : Write-enabled
R e s e r v e d b i t
M u s t a l w a y s b e s e t t o " 0 "
b 0
S y s t e m c l o c k c o n t r o l r e g i s t e r 1
[ A d d r e s s 0 0 0 7
] C M 1
1 6
R e s e r v e d b i t
M u s t a l w a y s b e s e t t o " 0 "
Main clock division select bit
b 7 b 6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
page 281 of 354
, 0 0 5 5
]
1 6
1 6
, 0 0 4 7
, 0 0 5 7
, 0 0 5 9
]
1 6
1 6
1 6
1 6
, 0 0 4 F
, 0 0 4 D
]
1 6
1 6
1 6
INTiIC(i=0 to 2)
b 7
b 0
S1RIC
0
S02BCNIC
I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t
Make sure that the interrupt priority level of the
interrupt which is used to cancel the wait mode is
higher than the processor interrupt priority (IPL) of
the routine where the WAIT instruction is executed.
Reserved bit
Must always be set to "0"
]
1 6
to 03DF
)
16
16
b 7
0 0
Wait mode
2. Power Control
[Address 005F
, 0044
, 005E
16
16
[Address 0048
]
16
[Address 0049
]
16
and 0007
) and
16
16
b 0
S y s t e m c l o c k c o n t r o l r e g i s t e r 0
[ A d d r e s s 0 0 0 6
] C M 0
1 6
Reserved bit
Must always be set to "0"
WAIT peripheral function clock stop bit (Note 2)
0 : Do not stop f
, f
, f
in wait mode
1
8
32
1 : Stop f
, f
, f
in wait mode
1
8
32
Port X
select bit
C
0 : I/O port
1 : X
-X
generation
CIN
COUT
Main clock (X
-X
) stop bit
IN
OUT
0 : On
1 : Off
Main clock division select bit 0
0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit (Note 1, Note 2)
0 : X
, X
IN
OUT
1 : X
, X
CIN
COUT
]
16
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