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4 MEMORY AND BUS
4.2 Bus Access Cycle
The CPU uses the system clock for bus access operations. First, "Bus access cycle," "Device size," and "Access
size" are defined as follows:
• Bus access cycle: One system clock period = 1 cycle
• Device size:
Bit width of the memory and peripheral circuits that can be accessed in one cycle
Access size designated by the CPU instructions (e.g., LDR Rt, [Rn] → 32-bit data transfer)
• Access size:
Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can
be accessed with an 8- or 16-bit instruction.
4.3 Flash Memory
The Flash memory is used to store application programs and data. Address 0x0 in the Flash area is defined as the
vector table base address by default, therefore a vector table must be located beginning from this address. For more
information on the vector table, refer to "Vector Table" in the "Interrupt" chapter.
4.3.1 Flash Memory Pin
Table 4.3.1.1 shows the Flash memory pin.
Pin name
V
PP
For the V
voltage, refer to "Recommended Operating Conditions, Flash programming voltage V
PP
trical Characteristics" chapter.
Note: Always leave the V
4.3.2 Flash Bus Access Cycle Setting
There is a limit of frequency to access the Flash memory with no wait cycle, therefore, the number of bus access
cycles for reading must be changed according to the system clock frequency. The number of bus access cycles for
reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than
the system clock.
4.3.3 Flash Programming
The Flash memory supports on-board programming, so it can be programmed using a flash loader. The V
can be supplied from either an external power supply or the internal voltage booster.
Be sure to connect C
between the V
VPP
externally or for generating the voltage when the internal power supply is used.
The V
pin must be left open except when programming the Flash memory. However, it is not necessary to discon-
PP
nect the wire when using Bridge Board (S5U1C31001L) to supply the V
power supply so that it will be supplied during Flash programming only.
4-2
Table 4.2.1 Number of Bus Access Cycles
Device size
Access size
8 bits
16 bits
32 bits
Table 4.3.1.1 Flash Memory Pin
I/O
Initial status
P
–
pin open except when programming the Flash memory.
PP
and V
pins for stabilizing the voltage when the V
SS
PP
Seiko Epson Corporation
Number of bus access
cycles
8 bits
16 bits
32 bits
8 bits
16 bits
32 bits
8 bits
16 bits
32 bits
Flash programming power supply
voltage, as Bridge Board controls the
PP
1
2
4
1
1
2
1
1
1
Function
" in the "Elec-
PP
PP
voltage is supplied
PP
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
voltage
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