Epson Arm S1C31 Series Manuals

Manuals and User Guides for Epson Arm S1C31 Series. We have 1 Epson Arm S1C31 Series manual available for free PDF download: Technical Manual

Epson Arm S1C31 Series Technical Manual (416 pages)

CMOS 32-BIT SINGLE CHIP MICROCONTROLLER

Brand: Epson | Category: Microcontrollers | Size: 11.19 MB

Table of Contents
4
Overview
16
Features
16
Block Diagram
19
Pins
20
Pin Configuration Diagram
20
Pin Descriptions
23
Power Supply, Reset, and Clocks
26
Power Generator (PWGA)
26
Overview
26
Pins
26
D1 Regulator Operation Mode
27
D1 Regulator Voltage Mode
27
System Reset Controller (SRC)
28
Overview
28
Input Pin
29
Reset Sources
29
Initialization Conditions (Reset Groups)
30
Clock Generator (CLG)
30
Overview
30
Input/Output Pins
31
Clock Sources
31
Operations
34
Operating Mode
39
Initial Boot Sequence
39
Transition between Operating Modes
39
Interrupts
41
Control Registers
41
PWGA Control Register
41
CLG System Clock Control Register
42
CLG Oscillation Control Register
43
CLG IOSC Control Register
44
CLG OSC1 Control Register
44
CLG OSC3 Control Register
45
CLG Interrupt Flag Register
47
CLG Interrupt Enable Register
47
CLG FOUT Control Register
48
CLG Oscillation Frequency Trimming Register 1
49
CLG Oscillation Frequency Trimming Register 2
49
CLG Oscillation Frequency Trimming Register 3
50
CPU and Debugger
51
Overview
51
Cpu
51
Debugger
51
List of Debugger Input/Output Pins
51
External Connection
51
Reference Documents
52
Memory and Bus
53
Overview
53
Bus Access Cycle
54
Flash Memory
54
Flash Memory Pin
54
Flash Bus Access Cycle Setting
54
Flash Programming
54
Ram
55
Peripheral Circuit Control Registers
55
System-Protect Function
61
Instruction Cache
61
Memory Mapped Access Area for External Flash Memory
61
Control Registers
61
System Protect Register
61
CACHE Control Register
61
FLASHC Flash Read Cycle Register
62
Interrupt
63
Overview
63
Vector Table
63
Vector Table Offset Address (VTOR)
65
Priority of Interrupts
65
Peripheral Circuit Interrupt Control
65
Nmi
66
DMA Controller (DMAC)
67
Overview
67
Operations
68
Initialization
68
Priority
68
Data Structure
68
Transfer Source End Pointer
69
Transfer Destination End Pointer
69
Control Data
69
DMA Transfer Mode
71
Basic Transfer
71
Auto-Request Transfer
71
Ping-Pong Transfer
72
Memory Scatter-Gather Transfer
73
Peripheral Scatter-Gather Transfer
74
DMA Transfer Cycle
75
Interrupts
75
Control Registers
76
DMAC Status Register
76
DMAC Configuration Register
76
DMAC Control Data Base Pointer Register
77
DMAC Alternate Control Data Base Pointer Register
77
DMAC Software Request Register
77
DMAC Request Mask Set Register
77
DMAC Request Mask Clear Register
78
DMAC Enable Set Register
78
DMAC Enable Clear Register
78
DMAC Primary-Alternate Set Register
78
S1C31D41 Technical Manual
78
Seiko Epson Corporation
78
DMAC Primary-Alternate Clear Register
79
DMAC Priority Set Register
79
DMAC Priority Clear Register
79
DMAC Error Interrupt Flag Register
79
DMAC Transfer Completion Interrupt Flag Register
80
DMAC Transfer Completion Interrupt Enable Set Register
80
DMAC Transfer Completion Interrupt Enable Clear Register
80
DMAC Error Interrupt Enable Set Register
80
DMAC Error Interrupt Enable Clear Register
81
O Ports (PPORT)
82
Overview
82
I/O Cell Structure and Functions
83
Schmitt Input
83
Over Voltage Tolerant Fail-Safe Type I/O Cell
84
Pull-Up/Pull-Down
84
CMOS Output and High Impedance State
84
Clock Settings
84
PPORT Operating Clock
84
Clock Supply in SLEEP Mode
84
Clock Supply During Debugging
85
Operations
85
Initialization
85
Port Input/Output Control
86
Interrupts
87
Control Registers
88
Px Port Data Register
88
Px Port Enable Register
88
Px Port Pull-Up/Down Control Register
89
Px Port Interrupt Flag Register
89
Px Port Interrupt Control Register
89
Px Port Chattering Filter Enable Register
90
Px Port Mode Select Register
90
Px Port Function Select Register
90
P Port Clock Control Register
91
P Port Interrupt Flag Group Register
92
Control Register and Port Function Configuration of this IC
93
P0 Port Group
93
P1 Port Group
95
P2 Port Group
97
P3 Port Group
100
P4 Port Group
102
P5 Port Group
104
P6 Port Group
106
Pd Port Group
108
Common Registers between Port Groups
109
Universal Port Multiplexer (UPMUX)
110
Overview
110
Peripheral Circuit I/O Function Assignment
110
Control Registers
111
Pxy-Xz Universal Port Multiplexer Setting Register
111
Watchdog Timer (WDT2)
112
Overview
112
Clock Settings
112
WDT2 Operating Clock
112
Clock Supply in DEBUG Mode
112
Operations
113
WDT2 Control
113
Operations in HALT and SLEEP Modes
114
Control Registers
114
WDT2 Clock Control Register
114
WDT2 Control Register
115
WDT2 Counter Compare Match Register
115
Real-Time Clock (RTCA)
117
Overview
117
Output Pin and External Connection
117
Output Pin
117
Clock Settings
118
RTCA Operating Clock
118
Theoretical Regulation Function
118
Operations
119
RTCA Control
119
Real-Time Clock Counter Operations
120
Stopwatch Control
120
Stopwatch Count-Up Pattern
120
Interrupts
121
Control Registers
122
RTCA Control Register (Low Byte)
122
RTCA Control Register (High Byte)
123
RTCA Second Alarm Register
123
RTCA Hour/Minute Alarm Register
124
RTCA Stopwatch Control Register
124
RTCA Second/1Hz Register
125
RTCA Hour/Minute Register
126
RTCA Month/Day Register
127
RTCA Year/Week Register
127
RTCA Interrupt Flag Register
128
RTCA Interrupt Enable Register
129
Supply Voltage Detector (SVD3)
131
Overview
131
Input Pins and External Connection
132
Input Pins
132
External Connection
132
Clock Settings
132
SVD3 Operating Clock
132
Clock Supply in SLEEP Mode
132
Clock Supply in DEBUG Mode
133
Operations
133
SVD3 Control
133
SVD3 Operations
134
SVD3 Interrupt and Reset
134
SVD3 Interrupt
134
SVD3 Reset
135
Control Registers
135
SVD3 Clock Control Register
135
SVD3 Control Register
136
SVD3 Status and Interrupt Flag Register
137
SVD3 Interrupt Enable Register
138
16-Bit Timers (T16)
139
Overview
139
Input Pin
139
Clock Settings
140
T16 Operating Clock
140
Clock Supply in SLEEP Mode
140
Clock Supply During Debugging
140
Event Counter Clock
140
Operations
140
Initialization
140
Counter Underflow
141
Operations in Repeat Mode
141
Operations in One-Shot Mode
141
Counter Value Read
142
Interrupt
142
Control Registers
142
T16 Ch.n Clock Control Register
142
T16 Ch.n Control Register
143
T16 Ch.n Reload Data Register
144
T16 Ch.n Counter Data Register
144
T16 Ch.n Interrupt Flag Register
144
T16 Ch.n Interrupt Enable Register
145
Uart (Uart3)
146
Overview
146
Input/Output Pins and External Connections
147
List of Input/Output Pins
147
External Connections
147
Input Pin Pull-Up Function
147
Output Pin Open-Drain Output Function
147
Input/Output Signal Inverting Function
147
Clock Settings
147
UART3 Operating Clock
147
Clock Supply in SLEEP Mode
148
Clock Supply During Debugging
148
Baud Rate Generator
148
Data Format
148
Operations
149
Initialization
149
Data Transmission
150
Data Reception
151
Irda Interface
152
Carrier Modulation
153
Receive Errors
154
Framing Error
154
Parity Error
154
Overrun Error
154
Interrupts
155
DMA Transfer Requests
155
Control Registers
156
UART3 Ch.n Clock Control Register
156
UART3 Ch.n Mode Register
156
UART3 Ch.n Baud-Rate Register
158
UART3 Ch.n Control Register
158
UART3 Ch.n Transmit Data Register
159
UART3 Ch.n Receive Data Register
159
UART3 Ch.n Status and Interrupt Flag Register
159
UART3 Ch.n Interrupt Enable Register
160
UART3 Ch.n Transmit Buffer Empty DMA Request Enable Register
161
UART3 Ch.n Receive Buffer One Byte Full DMA Request Enable Register
161
UART3 Ch.n Carrier Waveform Register
161
Synchronous Serial Interface (SPIA)
162
Overview
162
Input/Output Pins and External Connections
163
List of Input/Output Pins
163
External Connections
163
Pin Functions in Master Mode and Slave Mode
164
Input Pin Pull-Up/Pull-Down Function
164
Clock Settings
164
SPIA Operating Clock
164
Clock Supply During Debugging
165
SPI Clock (Spiclkn) Phase and Polarity
165
Data Format
166
Operations
166
Initialization
166
Data Transmission in Master Mode
167
Data Reception in Master Mode
169
Terminating Data Transfer in Master Mode
171
Data Transfer in Slave Mode
171
Terminating Data Transfer in Slave Mode
172
Interrupts
173
DMA Transfer Requests
174
Control Registers
174
SPIA Ch.n Mode Register
174
SPIA Ch.n Control Register
175
SPIA Ch.n Transmit Data Register
176
SPIA Ch.n Receive Data Register
176
SPIA Ch.n Interrupt Flag Register
176
SPIA Ch.n Interrupt Enable Register
177
SPIA Ch.n Transmit Buffer Empty DMA Request Enable Register
177
SPIA Ch.n Receive Buffer Full DMA Request Enable Register
177
Quad Synchronous Serial Interface (QSPI)
178
Overview
178
Input/Output Pins and External Connections
179
List of Input/Output Pins
179
External Connections
179
Pin Functions in Master Mode and Slave Mode
183
Input Pin Pull-Up/Pull-Down Function
183
Clock Settings
183
QSPI Operating Clock
183
Clock Supply During Debugging
184
QSPI Clock (Qspiclkn) Phase and Polarity
184
Data Format
185
Operations
186
Register Access Mode
186
Memory Mapped Access Mode
187
Initialization
188
Data Transmission in Master Mode
189
Data Reception in Register Access Master Mode
191
Data Reception in Memory Mapped Access Mode
194
Terminating Memory Mapped Access Operations
202
Terminating Data Transfer in Master Mode
202
Data Transfer in Slave Mode
203
Terminating Data Transfer in Slave Mode
204
Interrupts
204
DMA Transfer Requests
205
Control Registers
206
QSPI Ch.n Mode Register
206
QSPI Ch.n Control Register
208
QSPI Ch.n Transmit Data Register
209
QSPI Ch.n Receive Data Register
209
QSPI Ch.n Interrupt Flag Register
209
QSPI Ch.n Interrupt Enable Register
210
QSPI Ch.n Transmit Buffer Empty DMA Request Enable Register
210
QSPI Ch.n Receive Buffer Full DMA Request Enable Register
211
QSPI Ch.n FIFO Data Ready DMA Request Enable Register
211
QSPI Ch.n Remapping Start Address High Register
212
QSPI Ch.n Mode Byte Register
214
C (I2C)
215
Overview
215
Input/Output Pins and External Connections
216
List of Input/Output Pins
216
External Connections
216
Clock Settings
217
I2C Operating Clock
217
Clock Supply During Debugging
217
Baud Rate Generator
217
Operations
218
Initialization
218
Data Transmission in Master Mode
219
Data Reception in Master Mode
221
10-Bit Addressing in Master Mode
224
Data Transmission in Slave Mode
225
Data Reception in Slave Mode
227
Slave Operations in 10-Bit Address Mode
229
Automatic Bus Clearing Operation
229
Error Detection
230
Interrupts
231
DMA Transfer Requests
232
Control Registers
232
I2C Ch.n Clock Control Register
232
I2C Ch.n Mode Register
233
I2C Ch.n Baud-Rate Register
233
I2C Ch.n Own Address Register
234
I2C Ch.n Control Register
234
I2C Ch.n Transmit Data Register
235
I2C Ch.n Receive Data Register
235
I2C Ch.n Status and Interrupt Flag Register
236
I2C Ch.n Interrupt Enable Register
237
I2C Ch.n Transmit Buffer Empty DMA Request Enable Register
238
I2C Ch.n Receive Buffer Full DMA Request Enable Register
238
16-Bit PWM Timers (T16B)
239
Overview
239
Input/Output Pins
240
Clock Settings
241
T16B Operating Clock
241
Clock Supply in SLEEP Mode
241
Clock Supply During Debugging
241
Event Counter Clock
241
Operations
242
Initialization
242
Counter Block Operations
243
Comparator/Capture Block Operations
246
TOUT Output Control
255
Interrupt
261
DMA Transfer Requests
261
Control Registers
261
T16B Ch.n Clock Control Register
261
T16B Ch.n Max Counter Data Register
263
T16B Ch.n Timer Counter Data Register
263
T16B Ch.n Counter Status Register
264
T16B Ch.n Interrupt Flag Register
265
T16B Ch.n Interrupt Enable Register
266
T16B Ch.n Comparator/Capture M Control Register
267
T16B Ch.n Compare/Capture M Data Register
269
T16B Ch.n Counter Max/Zero DMA Request Enable Register
270
T16B Ch.n Compare/Capture M DMA Request Enable Register
270
IR Remote Controller (REMC3)
271
Overview
271
Output Pins and External Connections
271
List of Output Pins
271
External Connections
272
Clock Settings
272
REMC3 Operating Clock
272
Clock Supply in SLEEP Mode
272
Clock Supply During Debugging
272
Operations
272
Initialization
272
Data Transmission Procedures
273
REMO Output Waveform
273
Continuous Data Transmission and Compare Buffers
275
Interrupts
276
Application Example: Driving el Lamp
277
Control Registers
277
REMC3 Clock Control Register
277
REMC3 Data Bit Counter Control Register
278
REMC3 Data Bit Counter Register
279
REMC3 Data Bit Active Pulse Length Register
280
REMC3 Data Bit Length Register
280
REMC3 Status and Interrupt Flag Register
280
REMC3 Interrupt Enable Register
281
REMC3 Carrier Waveform Register
281
REMC3 Carrier Modulation Control Register
281
12-Bit A/D Converter (ADC12A)
283
Overview
283
Input Pins and External Connections
284
List of Input Pins
284
External Connections
284
Clock Settings
284
ADC12A Operating Clock
284
Sampling Time
284
Operations
285
Initialization
285
Conversion Start Trigger Source
285
Conversion Mode and Analog Input Pin Settings
286
A/D Conversion Operations and Control Procedures
286
Interrupts
288
DMA Transfer Requests
288
Control Registers
289
ADC12A Ch.n Control Register
289
ADC12A Ch.n Trigger/Analog Input Select Register
290
ADC12A Ch.n Configuration Register
291
ADC12A Ch.n Interrupt Flag Register
292
ADC12A Ch.n Interrupt Enable Register
292
ADC12A Ch.n DMA Request Enable Register M
293
ADC12A Ch.n Result Register
293
Temperature Sensor/Reference Voltage Generator (TSRVR)
294
Overview
294
Output Pin and External Connections
294
Output Pin
294
External Connections
295
Operations
295
Reference Voltage Setting
295
Temperature Sensor Setting
295
Control Registers
296
TSRVR Ch.n Temperature Sensor Control Register
296
TSRVR Ch.n Reference Voltage Generator Control Register
296
F Converter (RFC)
297
Overview
297
Input/Output Pins and External Connections
298
List of Input/Output Pins
298
External Connections
298
Clock Settings
299
RFC Operating Clock
299
Clock Supply in SLEEP Mode
299
Clock Supply in DEBUG Mode
299
Operations
299
Initialization
299
Operating Modes
300
RFC Counters
300
Converting Operations and Control Procedure
301
CR Oscillation Frequency Monitoring Function
303
Interrupts
303
Control Registers
304
RFC Ch.n Clock Control Register
304
RFC Ch.n Control Register
304
RFC Ch.n Oscillation Trigger Register
305
RFC Ch.n Measurement Counter Low and High Registers
306
RFC Ch.n Time Base Counter Low and High Registers
306
RFC Ch.n Interrupt Flag Register
307
RFC Ch.n Interrupt Enable Register
307
HW Processor (HWP) and Sound Output (SDAC2)
308
Overview
308
Output Pins and External Connections
309
List of Output Pins
309
HWP Operating Clock
311
Clock Supply in SLEEP Mode
311
Clock Supply in DEBUG Mode
311
Operations
312
Sound Play Function
312
Memory Check Function
320
External QSPI Flash Memory Access
324
Interrupts
325
HWP Internal Registers
325
Sound Play Function Registers
326
Function ID Register
326
Interrupt Mask Register
326
ROM Address Register
326
ROM Size Register
327
Key Code Register
327
N Command Register
327
N Sentence Number Setting Register
328
N Volume Control Register
328
N Repeat Control Register
328
0 Playback Speed Conversion Register
329
0 Playback Pitch Conversion Register
329
N State Monitor Register
330
Error Status Register
331
Operating Status Register
331
Version Number Register
331
Memory Check Function Register
332
Function ID Register
332
Interrupt Mask Register
332
Memory Address Register
332
Memory Size Register
333
Initial Value Setting Register
333
Command Register
333
State Monitor Register
333
Error Status Register
334
Operating Status Register
334
Calculation Result Register
334
Version Number Register
334
Control Registers
335
HWP Control Register
335
HWP Interrupt Flag Register
335
HWP Interrupt Enable Register
335
HWP Command Trigger Register
335
SDAC2 Clock Control Register
336
SDAC2 Control Register
336
SDAC2 Mode Register
337
SDAC2 Ch.n Data Register
337
SDAC2 Interrupt Flag Register
337
SDAC2 Interrupt Enable Register
338
SDAC2 Resampler Rate Register
338
SDAC2 Tone Divider Register
339
Electrical Characteristics
340
Current Consumption
341
System Reset Controller (SRC) Characteristics
344
Flash Memory Characteristics
347
Input/Output Port (PPORT) Characteristics
348
UART (UART3) Characteristics
351
Synchronous Serial Interface (SPIA) Characteristics
351
Quad Synchronous Serial Interface (QSPI) Characteristics
353
I C (I2C) Characteristics
353
12-Bit A/D Converter (ADC12A) Characteristics
354
Temperature Sensor/Reference Voltage Generator (TSRVR) Characteristics
355
Basic External Connection Diagram
358
Package
360
Appendix A List of Peripheral Circuit Control Registers
363
System Register (SYS)
363
Power Generator (PWGA)
363
Cache Controller (CACHE)
364
0X0020 00A0-0X0020 00A4 Watchdog Timer (WDT2)
365
0X0020 00C0-0X0020 00D2 Real-Time Clock (RTCA)
365
0X0020 0300-0X0020 031E Universal Port Multiplexer (UPMUX)
381
UART (UART3) Ch.0
383
0X0020 03C0-0X0020 03D6
386
0X0020 0400-0X0020 042C 16-Bit PWM Timer (T16B) Ch.0
387
0X0020 0440-0X0020 046C 16-Bit PWM Timer (T16B) Ch.1
389
0X0020 04C0-0X0020 04Cc 16-Bit Timer (T16) Ch.5
393
0X0020 04D0-0X0020 04De Synchronous Serial Interface (SPIA) Ch.2
393
UART (UART3) Ch.1
394
UART (UART3) Ch.2
395
0X0020 0670-0X0020 067E Synchronous Serial Interface (SPIA) Ch.1
397
0X0020 06C0-0X0020 06D6 I 2 C (I2C) Ch.1
399
0X0020 06E0-0X0020 06F6 I 2 C (I2C) Ch.2
401
0X0020 0780-0X0020 078C 16-Bit Timer (T16) Ch.7
403
0X0020 07A0-0X0020 07Bc 12-Bit A/D Converter (ADC12A) Ch.0
403
0X0020 07C0-0X0020 07C2 Temperature Sensor
404
Reference Voltage Generator (TSRVR) Ch.0
404
0X0020 0840-0X0020 0850 R/F Converter (RFC) Ch.0
405
0X0020 0860-0X0020 087E Sound DAC (SDAC2)
405
0X0020 1000-0X0020 2014 DMA Controller (DMAC)
407
Appendix B Power Saving
409
Operating Status Configuration Examples for Power Saving
409
Other Power Saving Methods
410
Appendix C Mounting Precautions
411
Appendix D Measures against Noise
413
Revision History
414

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