Table of Contents
Advertisement
21 HW Processor (HWP) and Sound Output
21.3 Clock Settings
21.3.1 HWP Operating Clock
The HWP, the SDAC and T16B Ch.0 used for the sound play function operate with the SYSCLK (system clock)
supplied from the clock generator. The HWP operating clock should be controlled as in the procedure shown below.
When executing the sound play function
1. Configure SYSCLK in the clock generator (refer to "Clock Generator" in the "Power Supply, Reset, and
Clocks" chapter).
- SYSCLK source = OSC3
- OSC3 oscillation frequency = 16 MHz
2. Set the following SDACCLK register bits (set in S1C31D50/D51 regardless of the sound output destination):
- Set the SDACCLK.CLKSRC[1:0] bits to 0x02. (Clock source = OSC3)
- Set the SDACCLK.CLKDIV[1:0] bits to 0x0.
3. Set the following T16B_0CLK register bits (only when outputting the sound signal from the T16B Ch.0
TOUT in S1C31D51):
- Set the T16B_0CLK.CLKSRC[2:0] bits to 0x02. (Clock source = OSC3)
- Set the T16B_0CLK.CLKDIV[3:0] bits to 0x0. (Clock division ratio = 1/1)
When executing the memory check function
1. Configure SYSCLK for operating the memory check function in the clock generator (refer to "Clock Gen-
erator" in the "Power Supply, Reset, and Clocks" chapter).
The memory check function allows the HWP to use SYSCLK at any arbitrary frequency.
21.3.2 Clock Supply in SLEEP Mode
The HWP and SDAC stop operating in SLEEP mode, as the SYSCLK stops. Do not put the IC into SLEEP mode
while the HWP is operating.
21.3.3 Clock Supply in DEBUG Mode
The sound play and memory check functions can operate even in DEBUG mode, as SYSCLK is supplied.
The SYSCLK supply to the SDAC during DEBUG mode can be controlled using the SDACCLK.DBRUN bit. The
SDACCLK.DBRUN bit must be set to 1 when using the sound play function during DEBUG mode. Be aware that
the sound cannot be output normally when SDACCLK.DBRUN bit = 0.
21.4 Operations
21.4.1 Sound Play Function
Initialization (when outputting sound from SDAC in S1C31D50/D51)
When outputting sound using the SDAC, initialize the SDAC and HWP in this order as shown below.
Initializing SDAC
1. If the SDAC output pins are configured for general-purpose ports, assign the SDAC output function to
the ports. (Refer to the "I/O Ports" chapter.)
- P5MODSEL register = (P5MODSEL & 0x00fc) | 0x0003
2. Configure the SDAC operating clock. (Refer to Section 21.3, "Clock Settings.")
- Set the SDACCLK.CLKSRC[1:0] bits to 0x02.
- Set the SDACCLK.CLKDIV[1:0] bits to 0x0.
- Set the SDACCLK.DBRUN bit to 1.
3. Set the SDACCTL.SDACEN bit to 1.
21-4
(Clock division ratio = 1/1)
Seiko Epson Corporation
(Clock source = OSC3)
(Clock division ratio = 1/1)
(Enable clock supply in DEBUG mode)
(Enable SDAC)
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Advertisement
Table of Contents
