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2
16 I
C (I2C)
16.1 Overview
The I2C is a subset of the I
2
• Functions as an I
2
C bus master (single master) or a slave device.
• Supports standard mode (up to 100 kbit/s) and fast mode (up to 400 kbit/s).
• Supports 7-bit and 10-bit address modes.
• Supports clock stretching.
• Includes a baud rate generator for generating the clock in master mode.
• No clock source is required to run the I2C in slave mode, as it can run with the I
• Slave mode is capable of being operated in SLEEP mode allowing wake-up by an interrupt when an address
match is detected.
• Master mode supports automatic bus clear sending function.
• Can generate receive buffer full, transmit buffer empty, and other interrupts.
• Can issue a DMA transfer request when a receive buffer full or a transmit buffer empty occurs.
Figure 16.1.1 shows the I2C configuration.
Item
Number of channels
I2C Ch.n
DMA
controller
TBEDMAENx
RBFDMAENx
CPU core
BYTEENDIE
GCIE
NACKIE
STOPIE
STARTIE
ERRIE
RBFIE
TBEIE
SFTRST
OADR10
OADR[9:0]
GCEN
MST
TXNACK
TXSTART
TXSTOP
CLKSRC[1:0]
CLKDIV[1:0]
Clock
DBRUN
generator
MODEN
CLK_I2Cn
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
C bus interface. The features of the I2C are listed below.
Table 16.1.1 I2C Channel Configuration of S1C31D50/D51
48-pin package
64-pin package
Receive data buffer
DMA request
control circuit
Transmit data buffer
BYTEENDIF
GCIF
NACKIF
Interrupt
STOPIF
control circuit
STARTIF
ERRIF
RBFIF
TBEIF
Transmit/receive
control circuit
Slave mode
Master mode
BRT[6:0]
Figure 16.1.1 I2C Configuration
Seiko Epson Corporation
80-pin package
3 channels (Ch.0 to Ch.2)
Shift register
RXD[7:0]
Shift register
TXD[7:0]
controller
controller
Baud rate
generator
16 I
C bus signals only.
2
100-pin package
V
SS
SDALOW
SCLLOW
BSY
TR
SCLO
V
SS
2
C (I2C)
SDAn
SCLn
16-1
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