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15 Quad Synchronous Serial Interface (QSPI)
QSPI Ch.n
16-bit timer
CLK_T16_m
Clock
generator
Timer
Underflow
TCSH[3:0]
RMADR[31:20]
DUMDL[3:0]
DUMLN[3:0]
DATTMOD[1:0]
DUMTMOD[1:0]
ADRTMOD[1:0]
ADRCYC
MMAEN
XIPACT[7:0]
XIPEXT[7:0]
MMABSY
CPU core
DMA
controller
15.2 Input/Output Pins and External Connections
15.2.1 List of Input/Output Pins
Table 15.2.1.1 lists the QSPI pins.
Pin name
QSDIOn[3:0]
QSPICLKn
#QSPISSn
If the port is shared with the QSPI pin and other functions, the QSPI input/output function must be assigned to the
port before activating the QSPI. For more information, refer to the "I/O Ports" chapter.
15.2.2 External Connections
The QSPI operates in master or slave mode. The memory mapped access mode is available only in master mode.
When QSPI Ch.n is operating in memory mapped access mode, the #QSPISSn output is controlled by the internal
state machine. In this case, only one external QSPI device can be connected.
When QSPI Ch.n is operating in register access master mode, the #QSPISSn output is directly controlled by a reg-
ister bit. In this case, GPIO pins other than #QSPISSn can also be used as the slave select output ports to connect
the QSPI to more than one external QSPI device.
Figures 15.2.2.1 to 15.2.2.7 show connection diagrams between the QSPI in each mode and external QSPI devices.
15-2
NOCLKDIV
CLK_QSPIn
1/2
BSY
MODEN
SFTRST
CHDL[3:0]
CHLN[3:0]
TMOD[1:0]
LSBFST
CPHA
Memory
CPOL
mapped access
control circuit
PUEN
DIR
MST
MSTSSO
OEIE
TENDIE
RBFIE
TBEIE
FRLDMAENx
RBFDMAENx
TBEDMAENx
Figure 15.1.1 QSPI Configuration
Table 15.2.1.1 List of QSPI Pins
I/O*
Initial status*
I or O
I (Hi-Z)
I or O
I (Hi-Z)
I or O
I (Hi-Z)
Seiko Epson Corporation
Shift registers
Transmit data buffer
Clock/shift
TXD[15:0]
register control
circuit
Receive data buffer
RXD[15:0]
Pull-up/down
control circuit
I/O and slave
select control
circuit
Interrupt
OEIF
TENDIF
control circuit
RBFIF
TBEIF
DMA request
control circuit
QSPI Ch.n data input/output pin
QSPI Ch.n external clock input/output pin
QSPI Ch.n slave select signal input/output pin
* Indicates the status when the pin is configured for the QSPI.
V
DD
QSDIOn[3:0]
V
DD
QSPICLKn
V
SS
V
DD
#QSPISSn
Function
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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