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15 Quad Synchronous Serial Interface (QSPI)
BIT
LENGTH = ——— [clocks]
N
Where
LENGTH: Data bit length [clocks]
BIT:
Number of transfer data bits
N:
1 (single transfer mode), 2 (dual transfer mode), or 4 (quad transfer mode)
15.5.2 Memory Mapped Access Mode
Memory mapped access mode is a low CPU overhead operation mode used with master mode to read data from
an external Flash memory, which supports XIP (eXecute-In-Place) mode. Once the external Flash memory enters
XIP mode and a read command is executed, the same read command operation can be performed by controlling the
slave select signal (inactive to active) and sending a new address to be accessed without the command being resent.
This may reduce command re-execution overhead and random access time.
An XIP session consists of a command cycle, an address cycle, a dummy cycle, and consecutive data cycles, and
it begins with an XIP specific read command similar to a general read command. Unlike a general read command,
one or more data lines must be driven to send XIP activation or termination confirmation bit(s) at the beginning of
the dummy cycle of an XIP session
In an XIP session, to start reading from a non-sequential Flash memory address, which is not continuous to the pre-
vious read address, assert the slave signal again after negating it once. After that, just send an address cycle to spec-
ify the new read start address and a dummy cycle including an XIP activation (continuation) confirmation bit(s),
as the command cycle is not needed in this XIP session. The Flash memory performs read operations the same as
the read command previously executed to execute a data cycle that includes a given number of data stored from the
newly specified address.
To terminate an XIP session, first assert the slave signal again after negating it once. Then, send an address cycle
with the address bits set to all high (suggested by most Flash memory manufacturers) and a dummy cycle including
an XIP termination confirmation bit(s) at the beginning of the cycle on one or more data lines. After that, negate the
slave select signal.
Figures 15.5.2.1 and 15.5.2.2 show Spansion S25FL128S Quad I/O Read command sequences as XIP operation
examples.
CS#
0
1
2
3
SCLK
8 cycles
Instruction
IO0
7
6
5
4
IO1
IO2
IO3
Figure 15.5.2.1 XIP Example - Spansion S25FL128S Quad I/O Read Command Sequence
15-10
4
5
6
7
8
24-bit address
3
2
1
0
20
21
22
23
The QSPI treats the dummy cycle as 8 cycles with 1 driving cycle.
(QSPI_nMOD.CHDL[3:0] bits = 0x0, QSPI_nMOD.CHLN[3:0] bits = 0x7)
(3-byte address, 0xeb [ExtAdd = 0], LC = 0b00)
Seiko Epson Corporation
12
13
14
15
16
17
6 cycles
2 cycles
4 cycles
Mode
Dummy
0
4
0
4
1
5
1
5
2
6
2
6
3
7
3
7
S1C31D50/D51 TECHNICAL MANUAL
(Eq. 15.2)
18
19
20
21
22
23
2 cycles
2 cycles
Data 1
Data 2
4
0
4
0
5
1
5
1
6
2
6
2
7
3
7
3
(Rev. 2.00)
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