Control Registers; Rfc Ch.n Clock Control Register; Rfc Ch.n Control Register - Epson S1C31D50 Technical Manual

20 R/F CONVERTER (RFC)

20.6 Control Registers

RFC Ch.n Clock Control Register

Register name Bit
RFC_nCLK 15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the RFC operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits select the division ratio of the RFC operating clock.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of the RFC.
RFC_nCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The RFC_nCLK register settings can be altered only when the RFC_nCTL.MODEN bit = 0.

RFC Ch.n Control Register

Register name Bit
RFC_nCTL 15–9 –
8
7
6
5–4 SMODE[1:0]
3–1 –
0
Bits 15–9 Reserved
Bit 8 RFCLKMD
This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock.
1 (R/W): Divided-by-two clock output
0 (R/W): Oscillation clock output
For more information, refer to "CR Oscillation Frequency Monitoring Function."
20-8
Bit name Initial
0x00
DBRUN 1
0x0
0x0
0x0
0x0
Table 20.6.1 Clock Source and Division Ratio Settings
0x0
IOSC
1/8
1/4
1/2
1/1
Bit name Initial
0x00
RFCLKMD 0
CONEN 0
EVTEN 0
0x0
0x0
MODEN 0
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W
– R
H0 R/W
– R
H0 R/W
RFC_nCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/1 1/8
1/4
1/2
1/1
Reset R/W
– R –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
– R
H0 R/W
S1C31D50/D51 TECHNICAL MANUAL
Remarks
0x3
EXOSC
1/1
Remarks
(Rev. 2.00)